GT-96100A Advanced Communication Controller
Revision 1.0
205
The two inbound queues allow external PCI agents to post inbound messages for the local MIPS CPU in one
queue and receive free messages (no longer in use) returning from the MIPS CPU. The process is as follows:
1. An external PCI agent posts an inbound message.
2. The MIPS CPU receives and processes the message.
3. When the processing is complete, the MIPS CPU places the message back into the inbound free queue
so that it may be reused.
8.7.2
Outbound message queues
There are two outbound message queues:
The Outbound Post queue is for messages from the MIPS CPU to other PCI agents to process.
The Outbound Free queue is for messages are from PCI agent to the MIPS CPU in response to an outgo-
ing message.
The two outbound queues allow the MIPS CPU to post outbound messages for external PCI agents in one queue
and receive free messages (no longer in use) returning from external PCI agents. The process is as follows:
1. The MIPS CPU posts an outbound message.
2. The external PCI agent receives and processes the message.
3. When the processing is complete, the external PCI agent places the message back into the outbound free
queue so that it may be reused.
8.7.3
Memory for Circular Queues
Data storage for the circular queues must be allocated in local SDRAM.
The base address for the queues is set in the Queue Base Address register (QBAR). Each queue entry is a 32-bit
data value. The circular queue sizes range from 4K entries (16Kbytes) to 64K entries (256Kbytes) yielding a
total local memory allotment of 64Kbytes to 1Mbyte. All four queues must be the same size and be contiguous in
the memory space. Queue size is set in the Queue Control register.
The starting address of each queue is based on the QBAR address and the size of the queues as shown in the table
below.
Table 211: Circular Queue Starting Addresses
Q ueu e
Starting Address
Inbound Free
QBAR
Inbound Post
QBAR + Queue Size
Outbound Post
QBAR + 2*Queue Size
Outbound Free
QBAR + 3*Queue Size