![](http://datasheet.mmic.net.cn/110000/GT-96100A_datasheet_3491740/GT-96100A_126.png)
GT-96100A Advanced Communication Controller
126
Revision 1.0
5.9
Memory Controller Restrictions
1. Unless the boot device is 64-bits wide, the boot must be on the even half (bits 31:0 of AD[63:0] bus).
2. When working with an 8- or 16-bit configured bank, a read/write operation can not exceed 64-bits (eight
bytes). Since PCI reads are always prefetchable, PCI access to a 8- or 16-bit wide device is not allowed
(unless FRAME* is asserted for a single PClk cycle).
3. When an erroneous address is issued or a burst operation is performed to an 8- or 16-bit device, the GT-
96100A forces an interrupt (unless masked). If a sequence of address misses occurs, there is no other
interrupt prior to resetting the appropriate bit in the cause register and no new address is registered in the
Address Decode Error register (0x470) prior to reading it.
4. When the CPU reads from an address which is decoded in the CPU Interface Unit as being a hit for
CS[2:0]* or BootCS* and CS[3]* and decoded as a miss in the SDRAM/Device Interface Unit, the
cycle completes only if Ready* is asserted (i.e., driven LOW).
Although being a result of improper and inconsistent programming of the address space defining regis-
ters, the following 2 workaround exist:
- Ready* must be asserted (LOW) when CSTiming* is inactive (HIGH).
- If the Ready* signal is not needed in the system, the Ready* pin must be driven active (LOW).
5. The minimum parameter for TurnOff, AccToFirst, AccToNext, WrActive, and WrHigh is 1 and for
ALEToWr is 3.
6. If address decode (register 0x47c) is set to 0, bursts of 64 bytes to 64-bit SDRAM are not supported.
Address decode mode 0 (0x47c) should not be used when using 64, 128, or 256Mbit SDRAMs.
7. PCI reads from 8- or 16-bit bank must not be prefetchable.
8. Access to SDRAM during SDRAM initialization time after reset results in unpredictable behavior.
9. When SDRAM CAS latency is 3, RAS precharge time (bit 3 of SDRAM parameter register) must be
programmed to 1.
10. When using 64/256 Mbit SDRAM, address decode 0 is not allowed.
11. In order for memory controller to return data of an internal register read, it must have control over the
AD bus.
12. When using aggressive prefetch, the highest address that can be read from the PCI is the last DRAM
address minus 0x8.
13.
Table 84 describes the limitation of a 32 bit device in the GT-96100A.