GT-96100A Advanced Communication Controller
298
Revision 1.0
16
RxBuffer-
Queue[0]
Rx Buffer Return in Priority Queue[0], Indicates a Rx buffer
returned to CPU ownership or that the port completed recep-
tion of a Rx frame in a receive priority queue[0]
0
17
RxBuffer-
Queue[1]
Rx Buffer Return in Priority Queue[1], Indicates a Rx buffer
returned to CPU ownership or that the port completed recep-
tion of a Rx frame in a receive priority queue[1]
0
18
RxBuffer-
Queue[2]
Rx Buffer Return in Priority Queue[2], Indicates a Rx buffer
returned to CPU ownership or that the port completed recep-
tion of a Rx frame in a receive priority queue[2]
0
19
RxBuffer-
Queue[3]
Rx Buffer Return in Priority Queue[3], Indicates a Rx buffer
returned to CPU ownership or that the port completed recep-
tion of a Rx frame in a receive priority queue[3]
0
20
RxError-
Queue[0]
Rx Resource Error in Priority Queue[0], Indicates a Rx
resource error event in receive priority queue[0]
0
21
RxError-
Queue[1]
Rx Resource Error in Priority Queue[1], Indicates a Rx
resource error event in receive priority queue[1]
0
22
RxError-
Queue[2]
Rx Resource Error in Priority Queue[2], Indicates a Rx
resource error event in receive priority queue[2]
0
23
RxError-
Queue[3]
Rx Resource Error in Priority Queue[3], Indicates a Rx
resource error event in receive priority queue[3]
0
27:24
Reserved
Reserved.
0
28
MIIPhySTC
MII PHY Status Change
Indicates a status change reported by the PHY connected to
this port.
Set when the MII management interface block identifies a
change in PHY’s register 1.
0
29
SMIdone
SMI Command Done
Indicates the SMI completed a MII management command
(either read or write) that was initiated by the CPU writing to
the SMI register.
0
30
Reserved
Reserved.
0
31
EtherIntSum
Ethernet Interrupt Summary
This bit is a logical OR of the (unmasked) bits [30:4] in the
Interrupt Cause register.
0
Table 298: Interrupt Cause Register (ICR), Offset: 0x084850 for
Ethernet_0; 0x088850 for Ethernet_1 (Continued)
Bits
Field Name
Fu nction
Initial Value