
GT-96100A Advanced Communication Controller
104
Revision 1.0
5.1.5
SDRAM Address Decode Register (0x47c)
The Address Decode Register is a three bit register which determines how bits of an address, presented on the
SysAD or PCI bus, are translated to row and column address bits on DAdr[12:0] and BankSel[1:0]. This flexibil-
ity allows the designer to choose the address decode setting. This gives the software the best chance This
improves the software’s capability of interleaving and enhancing overall system performance.
NOTE: The row and column address translation is different for 16 Mbit, 64/128 Mbit, 256 Mbit SDRAMs, 32-
bit and 64-bit SDRAM banks. The address decoding depends on the setting of AddrDecode. See
Table76 for the SRAS* and SCAS* address translation from the SysAD interface and PCI.
Table 72: SysAD/PCI Address Decoding for 32-bit SDRAM, 16 Mbit
Ad drDeco de,
0x47c
SysAD/PCI Bits used fo r
SRAS* o n Ban kSel[0],
DAd r[10:0]
SysAD/PCI Bits used fo r
SCAS* o n Ban kSel[0],
DAd r[10:0]
000
4, 21-11
4, “0”, 23-22, 10-5, 3-2
001
5, 21-11
5, “0”, 23-22, 10-6, 4-2
010
11, 21-12, 10
11, “0”, 23-22, 9-2
011
12, 21-13, 11-10
12, “0”, 23-22, 9-2
100
20, 21, 19-10
20, “0”, 23-22, 9-2
101
21, 20-10
21, “0”, 23-22, 9-2
110
22, 21-11
22, “0”, 23, 10-2 (only for x4 & x8)
111
23, 21-11
23, “0”, 22, 10-2 (only for x4)
Table 73: SysAD/PCI Address Decoding for 64-bit SDRAM, 256/512 Mbit
Ad drDeco de,
SysAD/PCI Bits used fo r
SRAS* o n Ban kSel[0],
BankSel[1], DAdr[12:0]
SysAD/PCI Bits used fo r
SCAS* o n Ban kSel[0],
BankSel[1], DAdr[12:0]
000
Illegal setting for 64, 128Mbit and 256Mbit SDRAM
001
6, 7, 25-13
6, 7, 29-28, “0”, 27-26, 12-8, 5-3
010
11, 12, 25-13
11, 12, 29-28, “0”, 27-26, 10-3
011
13, 14, 25-15, 12-11
13, 14, 29-28, “0”, 27-26, 10-3
100
21, 22, 25-23, 20-11
21, 22, 29-28, “0”, 27-26, 10-3
101
23, 24, 25, 22-11
23, 24, 29-28, “0”, 27-26, 10-3
110
24, 25, 23-11
24, 25, 29-28, “0”, 27-26, 10-3
111
25, 26, 27, 22-11
25, 26, 29-28, “0”, 24-23, 10-3