GT-96100A Advanced Communication Controller
Revision 1.0
167
7.8
64-bit PCI Configuration
The GT-96100A is configured to work as a 64-bit PCI device if DAdr[2] and FRAME1*/REQ64* pins are sam-
NOTE: The hold time for REQ64*, in respect to RST* rise, is 0, as required by the PCI spec.
When the GT-96100A is configured to a 64-bit PCI, both master and target interfaces are configured to execute
64-bit transactions, whenever possible.
The PCI master interface always attempts to generate 64-bit transactions (asserts REQ64#) except for I/O or con-
figuration transactions or when the required data is less than 64 bits. If the transaction target does not respond
with ACK64#, the master completes the transaction as a 32-bit transaction.
The PCI target interface always responds with ACK64# to a 64-bit transaction, except for accesses to configura-
tion space or internal registers.
NOTE: PClk1 must be tied to PClk0 on 64-bit PCI configuration.
7.9
Retry Enable
Some applications require that the local MIPS CPU program the PCI configuration registers in advance of other
bus masters accessing them. In a PC add-in card application, for example, the MIPS CPU must set the device ID,
BAR size requirements, etc. before the BIOS attempts to configure the card. The GT-96100A provides a mecha-
nism by which the PCI target interface retries all transactions until this configuration is complete. This prevents
race conditions between the local MIPS processor and the BIOS.
If DAdr[6] pin is sampled low on reset, the GT-96100A PCI target retries any transaction targeted to the GT-
96100A’s space. The GT-96100A stays in this retry mode until the Stop Retry bit in CPU configuration register
(0x000) is set to 1.
7.10
Locked Cycles
The GT-96100A locks a cache line (fixed at 32 bytes) in the local memory address space when responding to
Lock sequences on the PCI bus.
When a cache line is locked, any new PCI access to an address within the locked cache line (except accesses ini-
tiated by the LOCK owner) is terminated with RETRY. Also, every access from CPU or DMA to the locked
cache line is on hold until the LOCK ends.
Although the GT-96100A does not support the Lock* pin on PCI_1, any access from PCI_1 to a locked cache
line is not completed until the LOCK ends.