GT-96100A Advanced Communication Controller
Revision 1.0
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21.1.1 Communication Unit Cause Registers
The GT-96100A includes 16 second level cause registers used to trap events generated within the communication
unit.
Each interrupt source in the communication unit is tied to one of these second level cause registers. Each of these
registers is tied to specific bits in the High_Cause register and in the Serial_Cause register. These bits function as
summary bits, and are set when specific bits in the cause register are asserted (i.e. each summary bit is equivalent
to a logical OR of some bits in one of the cause registers). These summary bits are read-only.
When an interrupt event occurs in the communication unit, a bit is set in one of the second level cause registers.
This bit, if not masked, asserts one of the summary bits in the High_Cause register and in the Serial_Cause regis-
ter. Following that, one (or more) of the interrupt lines is asserted.
The CPU recognizes an interrupt that is due to the communication unit when one of the summary bits in the
High_Cause register is set or when one of the summary bits in the Serial_Cause register is set. Based on the spe-
cific bit set, the CPU reads the second level cause register associated with this bit in order to identify the actual
interrupt event that generated the interrupt. In order to acknowledge the interrupt, the CPU must write zero to this
bit in the cause register.
NOTE: The CPU cannot reset the summary bits directly, because these bits are read-only. A summary bit is
automatically reset when the CPU resets the bits in the related second level cause register.
21.2
Interrupt Mask Registers
The GT-96100A provides interrupt mask registers for each of the internal cause registers. These mask registers
allow masking of certain events, so that only specific events (as selected by the user) actually cause assertion of
one of the interrupts.
There are two mask registers associated with Interrupt0* and two mask registers associated with Interrupt1*.
These mask registers are used for enabling events that cause the assertion of either of these interrupts. For
Interrupt0*, these mask registers are located at 0x000C1C and at 0x000C9C. For Interrupt1*, the mask registers
are located at 0x000C24 and at 0x000C38. Programming ‘0’ in a mask register bit disables the associated event
from asserting interrupt. Programming ‘1’ allows the interrupt event to cause interrupt signal assertion.
In addition, there is one mask register associated with each of the serial interrupt pins. For SerInt0* the mask reg-
ister is located at 0x103A80 and for SerInt1* the mask register is located at 0x103A88.