GT-96100A Advanced Communication Controller
Revision 1.0
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Figure 9: CPU Four Word Burst Write
The GT-96100A transitions to the last-burst write data phase on the last datum of the transfer. This state is differ-
entiated from the mid-burst state by the WEOD command driven on the SysCmd bus. The last-burst data phase is
also entered for the datum written for a single word, or sub-word, write. On the clock cycle following WEOD,
the GT-96100A returns to the idle state.
NOTE: CPU writes cannot be issued as long as WrRdy* is deasserted (HIGH). If WrRdy* is high and an CPU
this protocol. Only DMA engines on the SysAD bus need to be concerned with sampling WrRdy*
before initiating a write.
4.3
Operation of WrRdy* and the Internal Write Posting Queues
The GT-96100A’s CPU interface includes a write posting queue that absorbs local CPU writes at zero wait-states.
This is required per the MIPs SysAD bus write protocol.
The write posting queue has four address entries and eight 64-bit data entries. The GT-96100A signals if there is
room in the CPU write posting queue by asserting WrRdy*. If WrRdy* is asserted, the CPU may issue a write of
up to eight words or four double words.
MIPs compliant processors such as the R4XXX/R5000/R7000 sample WrRdy* automatically before issuing a
write.
4.4
CPU Write Modes and Write Patterns Supported
The GT-96100A supports both pipelined and R4XXX/R5000/R7000 compatible write modes (with two dead
cycles between consecutive writes). The default mode is pipelined. However, the R4XXX mode can be selected
in the CPU Interface Configuration Register.
The CPU interface supports only DDDD and DXDXDXDX write patterns. One of these two write patterns must
be selected via the CPU serial initialization bitstream during the CPU reset process. Bit 16 of the CPU Interface
Configuration register (0x000) must be programmed according to the write pattern programming of the CPU.
NOTE: In the above explanation, ‘D’ represents data and ‘X’ is a wait state.
ADDR
WR4WORD
DATA 1&2
DATA 3&4
WEOD
TClk
ValidOut*
WrRdy*
SysAD[63:0]
SysCmd[8:0]
Release*
ValidIn*
ADDRESS PHASE
LAST-BURST PHASE
MID-BURST DATA
WRITE PHASE