GT-96100A Advanced Communication Controller
Revision 1.0
315
13.5
SDMA Group Configuration Register
Use this register to assign a specific SDMA channel from one of the SDMA groups to handle the data stream
associated with the corresponding MPSC.
NOTE: MPSC’s receive and transmit data flows does not have to be assigned to the same SDMA group. For
example, there is no problem with assigning MPSC0 transmit to SDMA channel 0 of group 0, while
MPSC0 receive flow is handled by SDMA channel 0 of group 1. Moreover, for certain asymmetric pro-
tocols, like ADSL, the bandwidth requirements for Rx and Tx are different, and splitting the data
streams between the SDMA groups may be critical for controlling bandwidth allocation.
31
AT
Abort Transmit
The CPU sets the AT bit to ‘1’ when it needs to abort a trans-
mit SDMA channel operation. When the AT bit is set, the
SDMA aborts its operation and goes to IDLE state. No
descriptor is closed. The GT-96100A clears both the AT and
TXD bits when entering IDLE state.
The CPU must poll bit 31. When it is ‘0’, the GT-96100A has
completed the abort sequence. After an abort, the CPU must
write the first descriptor address and than set TXD bit to ‘1’.
0
Table 318: SDMA Group Register (SGC), Offset: 0x101AF0
Bits
F ield Name
Functio n
In itial Value
7:0
RxSG[7:0]
Rx Group
These bits are used to assign one of the SDMA groups to
the RX data of each MPSC. RxSG[0] controls MPSC0,
RxSG[1] controls MPSC1 and so on.
0 - Receive data from the MPSC is handled by
SDMA group 0.
1 - Receive data from the MPSC is handled by
SDMA group 1.
0
15:8
TxSG[7:0]
Tx SDMA Group
These bits are used to assign one of the SDMA groups to
the TX data of each MPSC. TxSG[0] controls MPSC0,
TxSG[1] controls MPSC1 and so on.
0 - Transmit data to the MPSC is handled by
SDMA group 0.
1 - Transmit data to the MPSC is handled by
SDMA group 1.
0
31:16
Reserved
Reserved.
0
Table 317: SDMA Command Register (SDCMx), Offset: 0x000908 (Continued)
Bits
F ield Name
Fun ction
Initial Value