GT-96100A Advanced Communication Controller
Revision 1.0
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12.3
Operational Description
12.3.1 General Overview
The Ethernet unit provides multiple Ethernet ports functionality, with each port capable of running at either 10 or
100Mb/s (half or full-duplex) independently of the other port. Each port interfaces a MII PHY on its serial side
and manages packet data transfer between memory and MII. The data is stored in memory buffers, with any sin-
gle packet spanning multiple buffers if necessary. Upon completion of packet transmission or reception, a status
report, which includes error indications, is written by the Ethernet unit to the first or last descriptor associated
with this packet.
The buffers are allocated by the CPU and are managed through chained descriptor lists. Each descriptor points to
a single memory buffer and contains all the relevant information relating to that buffer (i.e. buffer size, buffer
pointer, etc.) and a pointer to the next descriptor. Data is read from buffer or written to the buffer according to
information contained in the descriptor. Whenever a new buffer is needed (end of buffer or end of packet), a new
descriptor is automatically fetched and the data movement operation is continued using the new buffer.
Figure 38 shows an example of memory arrangement for a single packet using three buffers.
Figure 38: Ethernet Descriptors and Buffers
The following sections provide detailed information about the operation and user interface of the Ethernet unit
and its logic subsections.
12.3.2 Transmit Operation
In order to initialize a transmit operation, the CPU must do the following:
1. Prepare a chained list of descriptors and packet buffers.
command/status
buffer pointer
next descriptor pointer
buffer size/byte count
0
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command/status
buffer pointer
next descriptor pointer
buffer size/byte count
0
31
packet 1 - buffer 1
packet 1 - buffer 2
command/status
buffer pointer
next descriptor pointer
buffer size/byte count
packet 1 - buffer 3
Descriptor 1
Descriptor 2
Descriptor 3