GT-96100A Advanced Communication Controller
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Revision 1.0
The GT-96100A becomes a PCI bus master when the CPU interface unit or the internal DMA engine initiates a
bus cycle to a PCI device. The following PCI bus cycles are supported:
Memory Read/Write
Interrupt Acknowledge
Special
I/O Read/Write
Configuration Read/Write
Locked Reads/Writes (only for PCI_0 slave).
The GT-96100A acts as a target when a PCI device initiates a memory access (or an I/O access in the case of
internal registers). It responds to all memory read/write accesses, as well as to all configuration and I/O cycles in
the case of internal registers. It is possible to program the PCI slave function to retry all PCI transactions targeted
to the GT-96100A. The PCI slave performs PCI address remapping to resources.
The GT-96100A includes all required PCI configuration registers. All internal registers, including PCI configura-
tion registers, are accessible from both the CPU bus and the PCI bus. GT-96100A configuration register set is PC
Plug-and-Play compatible, with industry standard I2O support.
The GT-96100A supports PCI Hot-Plug and CompactPCI Hot Swap Capable requirements.
The GT-96100A can also act as a PCI to Memory bridge and PCI communication peripheral, even without the
presence of a CPU.
1.5
Independent DMA (IDMA) Engines
The GT-96100A incorporates four high performance IDMA engines.
Each IDMA engine has the capability to transfer data between PCI devices, between PCI devices and main mem-
ory, or between devices residing on the 64-bit device/memory bus. The IDMA uses two internal 64-byte FIFOs
for temporary storage of IDMA data. These pair of FIFOs allows two IDMA channels to be working concur-
rently with each channel utilizing one FIFO. For example, while channel 0 is reading data from SDRAM into one
FIFO, channel 2 can write data from the other FIFO to the PCI bus.
Source and destination addresses can be nonaligned on any byte address boundary. The IDMA channels can be
controlled from the CPU or PCI interfaces or via a linked list of records without CPU bus intervention. This
linked list is loaded by the IDMA controller into the channel’s working set when a IDMA transaction ends. The
IDMA supports increment/decrement/hold on source and destination addresses independently and alignment of
addresses towards source and destination. In addition, the GT-96100A provides an override capability of source/
destination/record address mapping to force access to PCI_0 or PCI_1.
IDMA can be initiated by the CPU writing to a register, an external request via IDMAReq* pin, or an internal
timer/counter. Four End-of-Transfer pins, which act as inputs to the GT-96100A, allow ending a IDMA transfer
on a certain channel. In case of chained mode, it is possible to transfer the descriptor to CPU ownership after the
transfer has ended. The CPU then calculates the number of remaining bytes in the buffer associated with the
closed descriptor.
Fly-by is also supported. This mode allows data to be transferred directly between two residents on the device/
memory bus without having to go into an IDMA FIFO.