GT-96100A Advanced Communication Controller
34
Revision 1.0
ADP[0]/
EOT[0]*/
DAdr[12]
I/O
SDRAM data
ECC[0]
If the GT-96100A is configured for ECC mode, then in SDRAM
accesses, this pin serves as bit [0] of the ECC for data bits
[63:0]. ECC is generated by the GT-96100A for 64 bit SDRAM
writes, and read from SDRAM ECC bank for 64 bit SDRAM
reads.
End of DMA
Transfer [0]
If the GT-96100A is configured to non-ECC mode, then in
SDRAM accesses, this pin serves as End Of Transfer indication
for DMA channel 0.
SDRAM
Address [12]
ADP[0] can be configured to function as SDRAM Address [12]
CSTiming*
O
Chip Select
Timing
This signal is active (asserted low) for the number of cycles that
the device currently being accessed is programmed to. Used to
qualify CS[3:0]*, BootCS and DMAAck[3:0]* signals.
SoR
NOTE: Sampled on RESET to configure the GT-96100A prior to boot-up. See
ALE
O
Address Latch
Enable
This signal is asserted in the Device address phase and must
be used to latch the Address, BootCS*, CS[3:0]*, DevRW* and
DMAAck[3:0]* pins from the AD bus.
Ready*/
EOT[1]*
I
Ready
This input signal is used as a cycle extender
NOTE: When inactive during device access, the access is
extended until Ready* is asserted.
End Of Trans-
fer [1]
Ready* can be programmed to function as EOT[1]*. See
Sec-SoR
NOTE: Sampled on RESET to configure the GT-96100A prior to boot-up. See
BypsOE*/
MGNT*/DWr*
OBypass Out-
put Enable
If bypass mode is enabled, this signal controls the output
enable for bypass latches/buffers/switches. The bypass can be
used when a 64-bit read transaction is executed from the CPU.
Read data will be transferred directly to the CPU bus. See
TableMemory (AD)
bus Grant
If the GT-96100A is configured (at RESET) for UMA support,
this pin functions as Memory Grant. It is asserted in response to
MREQ*.
SDRAM Write
This pin can be programmed to function as DWr*. See
SectionLocal Address Total: 76
Table 9:
Local Address and Data Bus Pin Assignments (Continued)
Pin Name
Type
Full Name
Descriptio n