GT-96100A Advanced Communication Controller
82
Revision 1.0
4.8.1
Hardware Connections
When Multiple GT-96100A devices are enabled, the WrRdy*, ValidIn*, and ScDOE* signals have slightly differ-
ent functionality versus when only one GT-96100A is enabled.
4.8.2
MultiGT Bit In The CPU Configuration Register
When the MultiGT bit is SET, the CPU Interface address decoding reduces to:
If (SysAD[26:25] == ID) AND (it's a WRITE), the access is directed to the internal space of the CPU
Interface registers. Bits[11:0] define the specific register offset.
If (SysAD[26:25] == ID) AND (it's a READ) AND (SysAD[27] == 0), the access is directed to the
internal space of the CPU Interface registers. Bits[11:0] define the specific register offset.
If (SysAD[26:25] == ID) AND (it's a READ) AND (SysAD[27] == 1), the access is directed to
BootCS*. Since 0x0.1FC0.0000 implies SysAD[26:25] == 3, the GT 96100A holding the boot device
should be strapped to ID = 3.
NOTE: As long as MultiGT bit is SET, there is no access to PCI, SDRAM and Devices and DMA internal regis-
ters. Access is available only to the CPU interface internal registers and to boot ROM.
When the MultiGT bit is CLEARED, the CPU Interface resumes normal address decoding.
NOTE: After the MultiGT bit is CLEARED, WrReady*,ValidIn*, and ScDOE* signals still operate as sustained
3-state (STS) outputs.
Table 33: WrRdy*, ValidIn*, and ScDOE* Signal Multiple GT-96100A Functionality
Sig nal
Mu ltiple GT-96100A Fu nction ality
WrRdy*
An open-source output requiring a 4.7 KOhm pull-down resistor. All WrRdy* outputs from
the GT-96100A devices must be tied together to drive the CPU WrRdy* input.
WrRdy* is driven LOW for one cycle before floating the output.
ValidIn*
An open-drain output requiring a 4.7 KOhm pull-up resistor. All ValidIn* outputs from the GT-
96100A devices must be tied together to drive the CPU ValidIn* input.
ValidIn* is driven HIGH for one cycle before floating the output.
ScDOE*
An open-source output requiring a 4.7 KOhm pull-down resistor. All ScDOE* outputs from the
GT-96100A devices must be tied together to drive the CPU and Secondary cache inputs.
ScDOE* is driven LOW for one cycle before floating the outputs.