GT-96100A Advanced Communication Controller
Revision 1.0
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12.3.3.2 RX DMA Pointer Registers
The RX DMA employs two 32-bit pointer registers per queue: RxFDP and RxCDP.
RxFDP - RX DMA First Descriptor Pointer.
RxFDP is a 32-bit register used to point to the first descriptor of a receive packet. The CPU must initial-
ize this register before enabling DMA operation. The value used for initialization should be the address
of the first descriptor to use.
RxCDP - RX DMA Current Descriptor Pointer.
RxCDP is a 32-bit register used to point to the current descriptor of a receive packet. The CPU must ini-
tialize this register before enabling DMA operation. The value used for initialization should be the same
as the value used for initializing RxFDP (i.e. address of first descriptor to use).
12.3.3.3 Type of Service Queueing
The Type of Service queuing algorithm is based on the decoding of the DSCP field from the IP header. The
DSCP field is located in the 6-MSB bits of the second byte in the IP header (See
Figure 43). This field indexes
the 64 IPT Table entries, which reside in the GT-96100A Ethernet register space. The 2-bit priority output of this
table is referred to in the algorithm as tos_priority.
The tos_priority is valid only if the tos2prio enable bit 21 in the Ethernet Port Configuration Extend register,
referred to in the algorithm as tos2prio_en, is set.
If a VLAN tag exists in the packet, the VLAN priority tag is decoded from the 3-MSB bits of the 2nd word in the
VLAN tag. This field is the index to the 8 entries in the VPT Table, which reside in the GT-96100A Ethernet reg-
ister space. The 2-bit priority output of this table is referred to in the algorithm as vlan_priority.
The GT-96100A can decode BPDU and IGMP protocol packets. These packets are referred to in the algorithm as
frame_bpdu and frame_igmp respectively. Protocol detection is controlled by the SPAN and IGMP bits in the
Ethernet Port Configuration Extend register, referred to in the algorithm as bpdu_captue and igmp_capture
respectively.
BPDU and IGMP protocol packets are sent to the highest value queue unless protocol detection is turned off.
The PRIOrx Override bit in the Ethernet Port Configuration Extend register, referred to in the algorithm as
overide_priority, takes precedence over tos_priority or vlan_priority. If this bit is set, ALL packets (except
frame_bpdu and frame_igmp) are sent to the default_priority queue. The algorithm notation for the PRIOrx 2-
bit field in the Ethernet Port Configuration Extend register is default_priority.
The packet type is checked after checking the source address, VLAN tag (if it exists), and LLC-SNAP (if it
exists). The packet type is compared to 0x8100, referred to in the algorithm as vlan_type, or to 0x800, referred
to in the algorithm as ip_type. If vlan_type or ip_type with VALID tos_priority, or both, are found on the
packet, the packet is referred to in the algorithm as frame_tagged.
Broadcast packets, which are referred to in the algorithm as frame_broadcast and are not marked as
frame_tagged are also sent to the default_priority queue.
If the packet is marked as frame_tagged, the GT-96100A sends the packet to the tos_priority queue or
vlan_priority queue. If both tos_priority and vlan_priority are extracted from the packet, the GT-96100A
sends the packet to the higher value queue.