
GT-96100A Advanced Communication Controller
Revision 1.0
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The SysAD bus is synchronous with respect to TClk and is locked with respect to the AD bus. The SysAD bus
may be asynchronous with respect to the PCI bus or locked to the PCI bus for lower synchronization latency.
4.2
SysAD, SysADC, and SysCmd Buses
The SysAD and SysCmd bus protocol implemented by the GT-96100A is completely compatible with the 64-bit
Orion bus protocol used by the IDT R4xxx, R5000, and R7000 processors. The GT-96100A extends this protocol
to support bursts less than four 64-bit words. These extensions can be used by DMA engines on the SysAD bus
for more efficient use of the interface.
The SysAD[63:0] bus is a 64-bit multiplexed address/data bus. The local CPU drives address for a single cycle
then either drives data (for a write) or floats the bus in anticipation of returned data (for a read.)
SysADC[7:0] is valid during data cycles only. It provides parity information for data on the SysAD bus. SysADC
has the same timing as SysAD.
The SysCmd[8:0] bus conveys the following information about the transaction:
The direction (read/write).
The size (byte, short, word, multi-word).
The status of the data (good/bad/last.).
SysCmd is driven by the CPU (or other local master) during the address phase of a transaction (with direction/
size information) and for the duration of a write (with good/bad/last information.) The GT-96100A drives
SysCmd during the data phase of read transactions.
The encodings for SysCmd[8:0] are shown in the tables below.
NOTE: Many encodings are not defined. These encodings are reserved and must not be used. A summary of bit
usage is shown below.
Table 26: SysCmd Bit Summary
SysCmd Bit
Fu nct ion
SysCmd[8]
0 = Transaction information (read/write/size)
1 = Data information (good/bad/last)
SysCmd[7]
Indicates last data/not last data during data cycles.
NOTE: Must be 0 for address cycles.
SysCmd[6]
0 = Read transaction during address cycles
1 = Write transaction during address cycles
NOTE: Must be 0 for data cycles.
SysCmd[5]
Indicates error status for data cycles.
NOTE: Must be 0 for address cycles.