GT-96100A Advanced Communication Controller
Revision 1.0
29
PErr0*
I/O
STS
PCI_0 Parity
Error
Asserted when a data parity error is detected.
This pin features a sustained tristate output.
SErr0*
OD
PCI_0 System
Error
Asserted when a serious system error (not necessarily a PCI_0
error) is detected. SErr0* behavior in the GT-96100A is pro-
grammable (refer to PCI section for details).
This pin features an open-drain output.
PCI Bus 0 Total: 50
Table 7:
PCI Bus 1 Pin Assignments
Pin Name
Type
Full Name
Description
VREF1
I
PCI_1 Voltage
Reference
Must be connected directly to the 3.3V or the 5V power plane
depending on which voltage level PCI_1 supports.
NOTE: VREF0 and VREF1 can be completely independent
voltage levels.
PClk1
I
PCI_1 Clock
Provides the timing for PCI_1 transactions. The PCI_1 clock
range is between 0 and 66MHz.
Runs independently of PClk0.
Active only when PCI _1 is enabled.
NOTE: The PClk0 cycle must be higher than the TClk cycle
by at least 1ns. This clock frequency can be indepen-
PAD1[31:0]/
PAD0[63:32]
I/O
PCI_1
Address/Data
During the first clock of the transaction, PAD1[31:0] contains a
physical byte address (32 bits). During subsequent clock
cycles, PAD1[31:0] contains data.
PCI_0 (64 bit)
Address/Data
If PCI_0 is configured for 64 bit, these pins function as
PAD0[63:32] and carry the most significant 32 bits of data for
PCI_0 transactions.
CBE1[3:0]*/
CBE0[7:4]*
I/O
PCI_1 Com-
mand/Byte
Enable
During the address phase of the transaction, CBE1[3:0]* pro-
vide the PCI_1 bus command. During the data phase, these
lines provide the byte enables.
PCI_0 (64 bit)
Byte Enable
If PCI_0 is configured for 64 bit, these pins function as
CBE0[7:4]* and carry byte enables for the most significant 32
bits of PCI_0 data.
Par1/Par64
I/O
PCI_1 Parity
Calculated by the GT-96100A as an even parity bit for
PAD1[31:0] and CBE1[3:0]* lines.
PCI_0 (64 bit)
Parity
If PCI_0 is configured for 64 bit, this pin functions as Par64 and
carries even parity bit for PAD0[63:32] and CBE0[7:4]*.
Table 6:
PCI Bus 0 Pin Assignments (Continued)
Pin Name
Type
Full Name
Description