GT-96100A Advanced Communication Controller
Revision 1.0
461
24.3
Instruction Register (IR)
The Instruction register (IR) is a 4-bit two-stage register. It contains the command that is shifted in when the TAP
FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR outputs all four bits in parallel.
The GT-96100A supports the following instructions:
NOTE: Bi-directional pins can be programmed to be either input or output, depending on their control bit in the
Boundary Scan Register.
24.4
Bypass Register (BR)
The Bypass Register (BR) is a one-bit serial shift register that connects TDI to TDO when the IR holds the
Bypass command, and the TAP FSM is in the Shift-DR state. Data that is driven on the TDI input pin is shifted
out one cycle later on the TDO output pin. The Bypass Register is loaded with "0" when the TAP FSM is in the
Capture-DR state.
24.5
JTAG Scan Chain
The JTAG Scan Chain is a serial shift register that is used to sample and drive all of the GT-96100A pins during
the JTAG tests. It is a 216-bit deep shift register in the GT-96100A, thereby allowing it to sequentially access all
Table 427: Supported JTAG Instructions
Instruction
Co de
Descrip tion
HIGHZ
0011
Select the Bypass Register between TDI and TDO.
Sets the GT-96100A output pins to high-impedance state.
IDCODE
0010
Selects the Identification Register between TDI and TDO.
This 32-bit register is used to identify the GT-96100A device.
EXTEST
0000
Selects the Boundary Scan Register between TDI and TDO.
Output boundary scan register cells drive the output pins of
the GT-96100A. Input boundary scan register cell sample the
input pin of the GT-96100A.
SAMPLE/PRE-
LOAD
0001
Selects the Boundary Scan Register between TDI and TDO.
Sample input pins of the GT-96100A to input boundary scan
register cells. Preload output boundary scan register cells
with the Boundary Scan Register value.
BYPASS
1111
Selects the single bit Bypass Registers between TDI and
TDO. This allows for rapid data movement through an
untested device.