GT-96100A Advanced Communication Controller
Revision 1.0
33
AD[35:32]/
DMAAck
[3:0]*
I/O
Address/Data
[35:32]
In SDRAM/Device data phase, these pins function as data bits
[35:32].
DMA Acknowl-
edge[3:0]
In Device address phase, these pins function as DMA Acknowl-
edges and are valid (and should be latched). They need to be
qualified with the CSTiming* signal. Latching is done via ALE.
AD[31:0]
I/O
Address/
Data[31:0]
Multiplexed address and data bus to the SDRAM (data only)
and Devices (address and data).
ADP[7:6]/
SRAS*/
SCAS*
I/O
SDRAM data
ECC [7:6]
If the GT-96100A is configured for ECC mode, then in SDRAM
accesses, these pins serve as bits [7:6] of the ECC for data bits
[63:0]. ECC is generated by the GT-96100A for 64-bit SDRAM
writes, and read from SDRAM ECC bank for 64-bit SDRAM
reads.
SDRAM Row
Address
Strobe
ADP[7:6] can be configured to function as SRAS* on RESET.
SDRAM Col-
umn Address
Strobe
ADP[7:6] can be configured to function as SCAS* on RESET.
ADP[5]/
DAdr[11]
I/O
SDRAM data
ECC [5]
If the GT-96100A is configured for ECC mode, then in SDRAM
accesses this pin serve as bit [5] of the ECC for data bits [63:0].
ECC is generated by the GT-96100A for 64 bit SDRAM writes,
and read from SDRAM ECC bank for 64 bit SDRAM reads.
SDRAM
Address [11]
If the GT-96100A is configured to non-ECC mode, then in
SDRAM accesses this pin functions as SDRAM address bit[11].
ADP[4]/Bank
Sel[1]
I/O
SDRAM data
ECC [4]
If the GT-96100A is configured for ECC mode, then in SDRAM
accesses this pin serve as bit [4] of the ECC for data bits [63:0].
ECC is generated by the GT-96100A for 64 bit SDRAM writes,
and read from SDRAM ECC bank for 64 bit SDRAM reads.
SDRAM Bank
Select [1]
If the GT-96100A is configured to non-ECC mode, then in
SDRAM accesses, this pin functions as bank select bit[1].
ADP[3:1]/
EOT[3:1]*/
DWr*
I/O
SDRAM data
ECC [3:1]
If the GT-96100A is configured for ECC mode, then in SDRAM
accesses, these pins serve as bits [3:1] of the ECC for data bits
[63:0]. ECC is generated by the GT-96100A for 64 bit SDRAM
writes, and read from SDRAM ECC bank for 64 bit SDRAM
reads.
End of DMA
Transfer [3:1]
If the GT-96100A is configured to non-ECC mode, then in
SDRAM accesses, these pins serve as End Of Transfer indica-
tions for the DMA channels.
SDRAM Write
ADP[3] can be configured to function as DWr* on RESET. See
Table 9:
Local Address and Data Bus Pin Assignments (Continued)
Pin Name
Type
Full Name
Description