GT-96100A Advanced Communication Controller
Revision 1.0
153
Memory Write and Invalidate and Memory Read Line cycles are carried out when the transaction accessing PCI
memory space requests a data transfer equal to the PCI cache line size. In case the transfer initiator is a DMA
engine, the requested address must be cache line aligned. In case of write transaction, Memory Write and Invali-
date Enable bit in the Configuration Command register must be set. When the PCI cache line size is set equal to
0, the GT-96100A never issues Memory Write and Invalidate or Memory Read Line cycles.
Memory Read Multiple is carried out when the transaction accessing PCI memory space requests a data transfer
greater than the PCI cache line size.
As a master, the GT-96100A does not issue Dual Address cycles (DAC) or Lock cycles on the PCI.
The PCI posted write buffer in the GT-96100A permits the CPU to complete CPU-to-PCI memory writes even if
the PCI bus is busy. The posted data is written to the target PCI device when the PCI bus becomes available.
7.2.1
PCI Master CPU Address Space Decode and Translation
Local masters access the PCI space through the PCI_0/1 Memory 0, PCI_0/1 Memory 1, and PCI_0/1 I/O decod-
ers in CPU address space.
CPU accesses claimed by these decoders are translated into the appropriate PCI cycles by the appropriate PCI
interface (PCI_0 only in case of 64-bit PCI interface). The address seen on the CPU bus is copied directly to the
PCI bus (unless the CPU-to-PCI address remapping capability is enabled.) For example, if an access to
0x1200.0040 is programmed to be bridged as a memory read from PCI, the active PCI address for this cycle will
be 0x1200.0040.
7.2.2
PCI Master CPU Byte Swapping
All accesses to PCI space by the CPU can have the data byte order swapped as the data moves through the GT-
96100A. Byte swapping is turned on via the MByteSwap bit in the PCI Internal Command register (0xc00.)
When the GT-96100A is configured for 64-bit PCI mode, byte swapping occurs across all eight byte lanes when
the ByteSwap bit is set for PCI_0.