Intel XeonTM Processor MP
Datasheet
85
SM_DAT
I/O
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal provides
the single-bit mechanism for transferring data between SMBus devices.The processor
includes a 10k
pull-up resistor to SM_V
CC for this signal.
SM_EP_A[2:0]
I
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in conjunction
with the upper address bits in order to maintain unique addresses on the SMBus in a system
with multiple Intel Xeon processors. To set an SM_EP_A line high, a pull-up resistor should
be used that is no larger than 1 k
. The processor includes a 10k pull-down resistor to V
SS
foreachofthese signals.
SM_TS_A[1:0]
I
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses on the SMBus
in a system with multiple Intel Xeon processors.
The device’s addressing, as implemented, includes a Hi-Z state for both address pins. The
use of the Hi-Z state is achieved by leaving the input floating (unconnected).
SM_VCC
I
Provides power to the SMBus components on the Intel Xeon processor. In addition, this
supply must be present for future processors utilizing the 603-pin socket.
SM_WP
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to SM_VCC.The processor
includes a 10k
pull-down resistor to V
SS for this signal.
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by system logic. On
accepting a System Management Interrupt, processors save the current state and enter
System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs.
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-Grant
state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing
internal clock signals to all processor core units except the system bus and APIC units. The
processor continues to snoop bus transactions and service interrupts while in Stop-Grant
state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is
an asynchronous input.
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the
Test Access Port).
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input
needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial
output needed for JTAG specification support.
TESTHI[6:0]
I
For each processor, all TESTHI inputs must be connected to VCC through a 1K -10K
resistor for proper processor operation. TESTHI[3:0] and TESTHI[6:5] may all be tied
together at each processor and pulled up to VCC with asingle1K 4.7 K resistor if
desired. However, boundary scan test will not function if these pins are tied together.
TESTHI4 must always be pulled up independently from the other TESTHI pins. The
TESTHI pins must not be connected between system bus agents.
Table 33. Signal Definitions (Page 7 of 8)
Name
Type
Description