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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 39/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
29
Valid high and low levels are determined by the input buffers via comparing with a reference
voltage called GTLREF (known as VREF in previous documentation).
Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the system board using high precision voltage divider circuits. It is important that the
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
for the AGTL+ signal group traces is known and well-controlled. For more details on platform
design see the appropriate platform design guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum
values across the range of VCC.
3. GTLREF is generated from VCC on the baseboard by a voltage divider of 1% resistors. Refer to the appropriate
platform design guidelines for implementation details.
4. R
TT is the on-die termination resistance measured at V
OL of the AGTL+ output driver. Refer to the Intel Xeon Processor
Signal Integrity Models for I/V characteristics.
5. COMP resistors are provided by the baseboard with 1% resistors. See the appropriate platform design guidelines for
implementation details.
6. The VCC referred to in these specifications refers to instantaneous VCC.
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the processor core (pads).
See Chapter 5.0 for the Intel Xeon processor pin listing and signal definitions.
All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise
specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Intel Xeon processor MP in IBIS format. AGTL+ layout guidelines are also available in the
appropriate platform design guidelines.
Note:
Care should be taken to read all notes associated with a particular timing parameter.
Table 12. AGTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
GTLREF
Bus Reference Voltage
2/3 VCC -2%
2/3 VCC
2/3 VCC + 2%
V
2, 3, 6
RTT
Termination Resistance
36
41
46
4
COMP[1:0]
COMP Resistance
42.77
43.2
43.63
5
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