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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 108/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
91
7.0
Features
7.1
Power-On Configuration Options
The Intel XeonTM processor MP has several configuration options which are determined by
hardware.
The processors sample their hardware configuration at reset, on the active-to-inactive transition of
RESET#. The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another RESET#. All resets reconfigure the
processor(s); they do not distinguish between a “software” reset and a “power-on” reset.
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. These signals are used for bus frequency-to-core-ratio determination. See Table 2 for the supported settings. For
production units, the processor ignores requests for ratios higher than the maximum ratio it supports. For example, an
1.3 GHz processor will recognize ratios of 1/13 and lower. For more details, see Chapter 10.0.
7.2
Clock Control and Low Power States
The processor allows the use of AutoHALT, Stop-Grant, and Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 35 for a visual representation of the processor low power states.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in the Sleep state and
other processors in Normal or Stop-Grant states.
7.2.1
Normal State—State 1
This is the normal operating state for the processor.
Table 35. Power-On Configuration Option Pins
Configuration Option
Pin
1
Notes
Output tri state
SMI#
Execute BIST (Built-In Self Test)
INIT#
In Order Queue de-pipelining (set IOQ depth to 1)
A7#
Disable MCERR# observation
A9#
Disable BINIT# observation
A10#
APIC cluster ID (0-3)
A[12:11]#
Disable bus parking
A15#
Disable Hyper-Threading Technology
A31#
Bus frequency-to-core ratio
LINT[1:0], IGNNE#, A20M#
2
Symmetric agent arbitration ID
BR[3:0]#
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