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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 98/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
82
Datasheet
DBI[3:0]#
I/O
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The
DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will
invert the data bus signals if more than half the bits, within a 16-bit group, change logic
level in the next cycle.
DBSY#
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the
processor system bus to indicate that the data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the appropriate pins on all processor system
bus agents.
DEFER#
I
DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order
completion. Assertion of DEFER# is normally the responsibility of the addressed memory
or I/O agent. This signal must connect the appropriate pins of all processor system bus
agents.
DP[3:0]#
I/O
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are driven
by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all
processor system bus agents.
DRDY#
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid
data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to
insert idle clocks. This signal must connect the appropriate pins of all processor system bus
agents.
DSTBN[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
FERR#
O
FERR# (Floating-point Error) is asserted when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-point error
reporting.
GTLREF
I
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be
set at 2/3Vcc. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical
0ora logical 1.
HIT#
HITM#
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results.
Any system bus agent may assert both HIT# and HITM# together to indicate that it requires
asnoop stall, whichcan be continuedbyreassertingHIT#and HITM#together.
Since multiple agents may deliver snoop results at the same time, HIT# and HITM# are
wire-OR signals which must connect the appropriate pins of all processor system bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, HIT# and HITM# are activated on specific clock edges and
sampledonspecificclock edges.
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion
of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system
bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the assertion of RESET#,
BINIT#, or INIT#.
This signal does not have on-die termination and must be terminated at the end agent.
Table 33. Signal Definitions (Page 4 of 8)
Name
Type
Description
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI0#
D[15:0]#
DBI1#
D[31:16]#
DBI2#
D[47:32]#
DBI3#
D[63:48]#
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相关代理商/技术参数 |
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|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
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| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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