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参数资料
| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 13/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
11
1.0
Introduction
The Intel XeonTM processor MP is based on the Intel NetBurstTM microarchitecture that
operates at significantly higher clock speeds and delivers performance levels that are significantly
higher than previous generations of IA-32 processors. While based on the new Intel NetBurst
micro-architecture, it still maintains the tradition of compatibility with IA-32 software. The Intel
Xeon processor MP also introduces a groundbreaking new feature to multi-processing servers
called Hyper-Threading technology that enables each processor in the system to process multiple
software threads simultaneously enabling higher performance level on multi-threaded server
software.
The Intel NetBurst microarchitecture features include much higher clock speeds, a Rapid
Execution Engine, a 400 MHz system bus, and a new Integrated Three-Level Cache architecture.
The Intel NetBurst microarchitecture doubles the pipeline depth from previous generation
processors, allowing the processor to reach much higher core frequencies. The Rapid Execution
Engine allows the two integer ALUs in the processor to run at twice the core frequency, which
allows integer instructions to execute in one half the processor’s clock cycle. The 400 MHz system
bus is a quad-pumped bus running off a 100 MHz system bus clock making 3.2 GB per second data
transfer rates possible. The Integrated Three-Level cache architecture is designed for and balanced
with the Intel NetBurst microarchitecture to provide fast access to large instruction and data sets
commonly found in large enterprise server applications. This cache architecture includes a unique
Level 1Execution Trace Cache that stores 12K decoded micro-op instructions, which remove the
decoder from the main execution path, a Level 2 Advanced Transfer Cache of 256KB operating at
full processor speed and an Integrated Level 3 Cache of 1MB or 512KB providing fast, on-chip
access to large server data sets.
Another key feature of the Intel Xeon processor MP that is an industry first for general purpose
multi-processing, is Intel’s Hyper-Threading Technology. This technology allows the Intel Xeon
processor MP to appear as two logical processors to the operating system and applications allowing
each physical processor to support two software threads simultaneously without increasing the
processor’s execution resources. The result is increased utilization of those resources for improved
performance on multi-threaded server software. Hyper-Threading technology compliments multi-
processing by providing greater headroom for multi-threaded server software.
The Intel NetBurst microarchitecture has also improved some of the features introduced in
previous generations, including Advanced Dynamic Execution, enhanced floating point and multi-
media unit, and Streaming SIMD Extensions 2 (SSE2). Advanced Dynamic Execution improves
speculative execution and branch prediction internal to the processor. The floating point and multi-
media units have been improved by making the registers 128 bits wide and adding a separate
register for data movement. Finally, SSE2 adds 144 new instructions for double-precision floating
point, SIMD integer, and memory management.
Intel Xeon processor MP is intended for high performance multi-processing enterprise server
systems with up to four processors on one bus which can then be connected in clusters to provide 8,
16, 32-way and greater configurations. The Intel Xeon processor MP will be available at speeds of
1.40, 1.50 and 1.60GHz with options for 512 Kbyte or 1 Mbyte of integrated level-3 (L3) cache.
These processors also include manageability features, such as an OEM EEPROM and Processor
Information ROM which are accessed through a System Management Bus (SMBus) interface and
contain information relevant to the particular processor and system in which it is installed. In
addition, enhancements have been made to the Machine Check Architecture.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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