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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 21/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
12
Datasheet
Table 1.
Intel XeonTM Processor MP Features
As a result of integrating the caches into the processor silicon, a return to PGA (Pin-Grid Array)
style processor packaging is possible. The Intel Xeon processor MP is packaged in a 603-pin
micro-PGA package and utilizes a surface mount ZIF socket with 603 pins. New heatsinks,
heatsink retention mechanisms and sockets are required (versus previous processors in the
Intel
Pentium III XeonTM processor family). Heatsinks and retention mechanisms have been
designed with manufacturability as a high priority. Hence, mechanical assembly can be completed
from the top of the motherboard.
The processors use a new scalable system bus protocol, referred to as the “system bus” in this
document. The processor system bus utilizes a split-transaction, deferred reply protocol similar to
that of the P6 processor family system bus, but is not compatible with the P6 processor family
system bus. The system bus uses Source-Synchronous Transfer (SST) for address and data transfer
to improve performance. Whereas the P6 processor family transfers data once per bus clock, the
Intel Xeon processor transfers data four times per bus clock (4X data transfer rate). Along with the
4X data bus, the address bus delivers addresses two times per bus clock and is referred to as a
‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.
Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2
Gbytes/second (3200 Mbytes/sec). Finally, the system bus also introduces transactions that are
used to deliver interrupts.
Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in
the appropriate platform design guide (refer to Section 1.2).
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“System bus” refers to the interface between the processor, system core logic (a.k.a. the chipset
components), and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O. For this document, “system bus” is used as the generic term for the Intel Xeon
processor scalable system bus.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
Processors
Per Bus
L2 Advanced
Transfer
Cache
Integrated
Level 3
Cache
Manageability
Features
Intel NetBurstTM
Micro-Architecture
Intel
Hyper-
Threading
Technology
Intel XeonTM
Processor MP
1-4
256 KB
512 KB or
1MB
Yes
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相关代理商/技术参数 |
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