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参数资料
| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 7/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
104
Datasheet
7.4.6.5
Conversion Rate Registers
The contents of the Conversion Rate Registers determine the nominal rate at which analog to
digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two
Conversion Rate Registers, RCR for reading the conversion rate value and WCR for writing the
value. Table 48 shows the mapping between Conversion Rate Register values and the conversion
rate. As indicated in Table 44, the Conversion Rate Register is set to its default state of 02h
(0.25 Hz nominally) when the thermal sensor is powered up. There is a ±30% error tolerance
between the conversion rate indicated in the conversion rate register and the actual conversion rate.
Table 48. SMBus Thermal Sensor Conversion Rate Registers
7.4.7
SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus
when a fault condition exists. The fault conditions consist of: 1) a processor thermal diode value
measurement that exceeds a user-defined high or low threshold programmed into the Command
Register or 2) disconnection of the processor thermal diode from the thermal sensor. The interrupt
can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the
system board via the SM_ALERT# open drain output. Once latched, the SM_ALERT# should only
be cleared by reading the Alert Response byte from the Alert Response Address of the thermal
sensor. The Alert Response Address is a special slave address shown in Table 43.The
SM_ALERT# will be cleared once the SMBus master device reads the slave ARA unless the fault
condition persists. Reading the Status Register or setting the mask bit within the Configuration
Register does not clear the interrupt.
7.4.8
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of the form
“1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors on the system
baseboard. These address pins are pulled down weakly (10 K
) on the processor substrate to
ensure that the memory components are in a known state in systems which do not support the
SMBus, or only support a partial implementation. The “Z” bit is the read/write bit for the serial bus
transaction.
Register Value
Conversion Rate (Hz)
00h
0.0625
01h
0.125
02h
0.25
03h
0.5
04h
1.0
05h
2.0
06h
4.0
07h
8.0
08h to FFh
Reserved for future use
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相关代理商/技术参数 |
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|---|---|
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| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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