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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 44/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
33
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins. All TAP signal
timings (TMS, TDI, etc) are referenced at GTLREF at the processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. TRST# must be held asserted for 2 TCK periods to be guarantee that it is recognized by the processor.
8. Specification for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of 0.5V/ns.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All AC timings for the SMBus signals are referenced at VIL_MAX or VIL_MIN and measured at the processor pins. Refer
to Figure 14.
4. Minimum time allowed between request cycles.
5. Rise time is measured from (VIL_MAX -0.15V)to(VIH_MIN + 0.15V). Fall time is measured from (0.9 * SM_VCC) to
6. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next transaction.
T63: TDO Clock to Output Delay
0.5
3.5
ns
6
T64: TRST# Assert Time
2
TTCK
7
Table 18. TAP Signal Group AC Specifications (Page 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3,9
Table 19. SMBus Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3
T70: SM_CLK Frequency
10
100
KHz
T71: SM_CLK Period
10
100
us
T72: SM_CLK High Time
4.0
N/A
us
T73: SM_CLK Low Time
4.7
N/A
us
T74: SMBus Rise Time
0.02
1.0
us
5
T75: SMBus Fall Time
0.02
0.3
us
5
T76: SMBus Output Valid Delay
0.1
4.5
us
T77: SMBus Input Setup Time
250
N/A
ns
T78: SMBus Input Hold Time
300
N/A
ns
T79: Bus Free Time
4.7
N/A
us
4, 6
T80: Hold Time after Repeated Start Condition
4.0
N/A
us
T81: Repeated Start Condition Setup Time
4.7
N/A
us
T82: Stop Condition Setup Time
4.0
N/A
us
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