Intel XeonTM Processor MP
Datasheet
15
2.0
Electrical Specifications
2.1
System Bus and GTLREF
Most processor system bus signals use Assisted Gunning Transceiver Logic + (AGTL+) signalling
technology. This signalling technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Unlike the Intel
Pentium III XeonTM
processor family, the termination voltage level for the Intel XeonTM processor MP AGTL+
signals is V
CC, the operating voltage of the processor core. P6 family processors utilize a fixed
1.5V termination voltage known as VTT . The use of a termination voltage that is determined by the
processor core allows better voltage scaling on the Intel NetBurstTM micro-architecture system
bus. Because of the speed improvements to data and address busses, signal integrity and platform
design methods become more critical than with previous processor families. Design guidelines for
the processor system bus are detailed in the appropriate platform design guidelines (refer to
SectionThe AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board
(See
Table 12 for GTLREF specifications). Termination resistors are provided on the processor
silicon and are terminated to its core voltage (V
CC). The on-die termination resistors are a
selectable feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die
termination can be enabled to control reflections on the transmission line. For middle bus agents,
on-die termination must be disabled. Intel chipsets will also provide on-die termination, thus
eliminating the need to terminate the bus on the system board for most AGTL+ signals.
Note:
Some AGTL+ signals do not include on-die termination and must be terminated on the system
board. See
Table 4 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus, including trace lengths, is highly recommended when designing a system. The Intel
XeonTM Processor Signal Integrity Models, are available at http://developer.intel.com
2.2
Power and Ground Pins
For clean on-chip power distribution, Intel Xeon processor MP have 155 V
CC (power) and 155 VSS
(ground) inputs. All power pins must be connected to VCC, while all VSS pins must be connected to
the system ground plane. The processor V
CC pins must be supplied the voltage determined by the
VID (Voltage ID) pins.
2.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large instantaneous current swings between low and full power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Larger bulk storage (C
BULK), such as electrolytic capacitors, supply current during longer lasting
changes in current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running condition.