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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 94/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
79
5.2
Signal Definitions
Table 33. Signal Definitions (Page 1 of 8)
Name
Type
Description
A[35:3]#
I/O
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the
address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins
transmit transaction type information. These signals must connect the appropriate pins of all
agents on the Intel Xeon processor system bus. A[35:3]# are protected by parity signals
AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset of the
A[35:3]# pins to determine their power-on configuration. See Section 7.1.
A20M#
I
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20
(A20#) before looking up a line in any internal cache and before driving a read/write
transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following
an I/O write instruction, it must be valid along with the TRDY# assertion of the
corresponding I/O write bus transaction
This signal is also sampledonthe deassertionofRESET#toset the core-to-system bus
frequency ratio. See Section 2.4 and Chapter 10.0 for more details.
ADS#
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the
A[35:3]# pins. All bus agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred reply ID match operations
associated with the new transaction. This signal must connect the appropriate pins on all
processor system bus agents.
ADSTB[1:0]#
I/O
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edge.
AP[1:0]#
I/O
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#,
andthe transactiontypeonthe REQ[4:0]#pins. Acorrect parity signal is high if an even
number of covered signals are low and low if an odd number of covered signals are low.
This allows parity to be high when all the covered signals are high. AP[1:0]# should connect
the appropriate pins of all Intel Xeon processor MP system bus agents. The following table
defines the coverage model of these signals.
BCLK[1:0]
I
The differential pair BCLK (Bus Clock) determines the bus frequency. All processor system
bus agents must receive these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of BCLK0
crossing the falling edge of BCLK1.
Request Signals
Subphase 1
Subphase 2
A[35:24]#
AP0#
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
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相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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