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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 19/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
115
10.0
Appendix A
10.1
Processor Core Frequency Determination
To allow system debug and multiprocessor configuration flexibility, the core frequency of the
Intel XeonTM processor MP is configured during the active-to-inactive edge of RESET# by using
the A20M#, IGNNE#, LINT[1]/NMI, and LINT[0]/INTR pins. The value on these pins during the
release of RESET# (see Section 2.12 for setup and hold time requirements) determines the
multiplier that the PLL will use for the internal core clock (see Table 2). See Section 5.2 for details
regarding the operation of these pins after Reset.
See Figure 40 for the timing relationship between the system bus multiplier signals, RESET#,
CRESET#, and normal processor operation. CRESET# (Configuration Reset) is a delayed copy of
system bus Reset signal. This signal is used to control the multiplexer for the processor frequency
configuration pins listed above. CRESET# is delayed from the system bus reset by two host clocks.
UsingCRESET# andthe timing shownin Figure 40, the circuit in Figure 41 can be used to share
these configuration signals. The component used as the multiplexer must not have outputs that
drive higher than V
CC in order to meet processor asynchronous GTL+ buffer specifications listed in
Table 10. The multiplexer output current should be limited to 200 mA maximum, in case the VCC
supply to the processor ever fails.
As shown in Figure 41, the pull-up resistors between the multiplexer and the processor force a
“safe” ratio into the processor in the event that the processor powers up before the multiplexer and/
or core logic. This prevents the processor from ever seeing a ratio higher than the final ratio.
The compatibility inputs to the multiplexer must meet the input specifications of the multiplexer.
This may require a level translation before the multiplexer inputs unless the inputs and the signals
driving them are already compatible.
The system bus frequency multipliers supported are shown in Table 2; other combinations will not
be validated nor are they authorized for implementation.
Clock multiplying within the processor is provided by the internal Phase Lock Loop (PLL), which
requires a constant frequency BCLK inputs. For Spread Spectrum Clocking, please refer to the
CK00 Clock Synthesizer/Driver Design Guidelines. The system bus frequency ratio cannot be
changed dynamically during normal operation, nor can it be changed during any low power modes.
The system bus frequency ratio can be changed when RESET# is active, assuming that all Reset
specifications are met.
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相关代理商/技术参数 |
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|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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