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参数资料
型号： YF80528KC017512
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603
封装： MICRO, PGA-603
文件页数： 33/116页
文件大小： 2277K
代理商： YF80528KC017512
Intel XeonTM Processor MP
Datasheet
23
2.8
Asynchronous GTL+ Signals
The Intel Xeon processor MP does not utilize CMOS voltage levels on any signals that connect to
the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output
FERR# and other non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+
output buffers. All of these asynchronous GTL+ signals follow the same DC requirements as
AGTL+ signals, however the outputs are not driven high (during the electrical low-to-high
transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous
GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all
of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for
the processor to recognize them. See Table 10 and Table 16 for the DC and AC specifications for
the asynchronous GTL+ signal group. See Section 7.2 for additional timing requirements for
entering and leaving low power states.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Intel Xeon processor MP be first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect to the rest of the
chain unless one of the other components is capable of accepting an input of the appropriate
voltage. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each
signal may be required with each driving a different voltage level. Refer to Chapter 9.0 for more
detailed information. See Table 9 and Table 18 for the DC and AC specifications for the TAP signal
group.
2.10
Maximum Ratings
Table 5 lists the processor’s maximum environmental stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from electro-
static discharge, one should always take precautions to avoid high static voltages or electric fields.
Table 5.
Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
T
STORAGE
Processor storage temperature
–40
85
°C
1
V
CC
Any processor supply voltage with
respect to VSS
–0.5
2.1
V
2
V
inAGTL+
AGTL+ buffer DC input voltage with
respect to VSS
–0.3
2.1
V
inGTL+
Async GTL+ buffer DC input voltage
with respect to VSS
-0.3
2.1
V
inSMBus
SMBus buffer DC input voltage with
respect to VSS
-0.3
6.0
V
I
VID
MaxVID pincurrent
5
mA
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