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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 31/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
21
2.6
Reserved Or Unused Pins
All Reserved pins must remain unconnected. Connection of these pins to VCC,VSS, or to any other
signal (including each other) can result in component malfunction or incompatibility with future
Intel Xeon processor MP. See Chapter 5.0 for a pin listing of the processor and the location of all
Reserved pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination is provided by the processor to allow end
agents to be terminated within the processor silicon. In this context, end agent refers to the bus
agent that resides on either end of the daisy-chained system bus interface while a middle agent is
any bus agent in between the two end agents. For end agents, most unused AGTL+ inputs should be
left as no connects, as AGTL+ termination is provided on the processor silicon. However, see Table
4 for details on AGTL+ signals that do not include on-die termination. For middle agents, the on-
die termination must be disabled, so the platform must ensure that unused AGTL+ input signals
which do not connect to end agents are connected to V
CC via a pull-up resistor. Unused active high
inputs, should be connected through a resistor to ground (V
SS). Unused outputs may be left
unconnected, however this may interfere with some TAP functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
For unused AGTL+ input or I/O signals, use pull-up resistors of the same value as the on-die
termination resistors (R
TT). See Table 12.
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the system board. Unused outputs
may be terminated on the system board or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing. Signal termination recommendations for these signal types is discussed in
the platform design guidelines and the ITP700 Debug Port Design Guide (see Section 1.2).
For each processor, all TESTHI[6:0] pins must be connected to VCC via a pull-up resistor of
between 1 k
and 10 k value. TESTHI[3:0] and TESTHI[6:5] may all be tied together at each
processor and pulled up to V
CC with a single 1 k 4.7 k resistor if desired. However, utilization
of boundary scan test will not be functional if these pins are connected together. TESTHI4 must
always be pulled up independently from the other TESTHI pins. The TESTHI pins must not be
connected between system bus agents.
2.7
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 4 identifies which signals are common
clock, source synchronous and asynchronous.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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