Intel XeonTM Processor MP
30
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The Intel Xeon processor MP core clock frequency is derived from BCLK. The bus clock to Intel Xeon processor MP
core clock ratio is determined during initialization as described in
Section 2.4.
Table 2 shows the supported ratios for the
3. The period specified here is the average period. A given period may vary from this specification as governed by the
period stability specification (T2).
4. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
5. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In
other words, the largest absolute difference between adjacent clock periods must be less than the period stability.
6. Slew rate is measured between the 35% and 65% points of the clock swing (VL and VH).
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
CROSS) ofthe BCLK[1:0]at
rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.
4. Valid delay timings for these signals are specified into the test circuit described in
Figure 3 andwithGTLREF at
2/3 VCC ± 2%.
5. Specification is for a minimum swing defined between AGTL+ V
IL_MAX to VIH_MIN.Thisassumesan edge rate of 0.4 V/
ns to 4.0 V/ns.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 13. System Bus Differential Clock Specifications
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
1
System Bus Frequency
100.0
MHz
2
T1: BCLK[1:0] Period
10.00
10.20
ns
3
T2: BCLK[1:0] Period Stability
N/A
150
ps
4, 5
T3: TPH BCLK[1:0] Pulse High Time
3.94
5
6.12
ns
T4: TPL BCLK[1:0] Pulse Low Time
3.94
5
6.12
ns
T5: BCLK[1:0] Rise Time
175
700
ps
6
T6: BCLK[1:0] Fall Time
175
700
ps
6
Table 14. System Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes 1, 2, 3
T10: Common Clock Output Valid Delay
0.20
1.45
ns
4
T11: Common Clock Input Setup Time
0.65
N/A
ns
5
T12: Common Clock Input Hold Time
0.40
N/A
ns
5
T13: RESET# Pulse Width
1.00
10.00
ms
6, 7, 8