参数资料
型号: YF80528KC017512
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603
封装: MICRO, PGA-603
文件页数: 45/116页
文件大小: 2277K
代理商: YF80528KC017512
Intel XeonTM Processor MP
34
Datasheet
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 13 through Table
Note:
For Figure 4 through Figure 12, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core (pads).
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated
strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+
strobe signal timings are referenced at GTLREF at the processor core (pads).
4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * VCC at the
processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5 * VCC at the
processor core (pads).
5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC
at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc) are referenced
at V
IL_MAX or VIL_MIN at the processor pins.
Figure 3. Electrical Test Circuit
600 mils, 42 ohms, 169 ps/in
2.4nH
1.2pF
V
CC
V
CC
R
load
Rload
= 50 ohms
AC Timings specified
at this point
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