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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 42/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
Datasheet
31
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data
signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are
referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal
timings are referenced at GTLREF at the processor core.
4. Unless otherwise noted, these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 3 andwithGTLREFat
2/3 VCC ± 2%.
6. Specification is for a minimum swing defined between AGTL+ V
IL_MAX to VIH_MIN.This assumes an edgerateof0.3 V/ns
to 4.0V/ns.
7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective
strobe.
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the
appropriate platform design guidelines for more information on the definitions and use of these specifications.
9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the appropriate
platform design guidelines for more information on the definitions and use of these specifications.
10. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#.
11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12. The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first
falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (5
ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must come approximately 3/4
BCLK period (7.5 ns) after the first falling edge of DSTBp#.
13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
14. This specification reflects a typical value, not a minimum or maximum.
Table 15. System Bus Source Synchronous AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2, 3, 4
T20: Source Sync. Output Valid Delay (first data/address
only)
0.20
1.30
ns
5
T21: TVBD Source Sync. Data Output Valid Before Data
Strobe
0.85
ns
5, 8
T22: TVAD Source Sync. Data Output Valid After Data
Strobe
0.85
ns
5, 8
T23: TVBA Source Sync. Address Output Valid Before
Address Strobe
1.88
ns
5, 8
T24: TVAA Source Sync. Address Output Valid After
Address Strobe
1.88
ns
5, 9
T25: TSUSS Source Sync. Input Setup Time
0.21
ns
6
T26: THSS Source Sync. Input Hold Time
0.21
ns
6
T27: TSUCC Source Sync. Input Setup Time to BCLK
0.65
ns
7
T28: TFASS First Address Strobe to Second Address
Strobe
1/2
BCLKs
10, 14
T29: TFDSS: First Data Strobe to Subsequent Strobes
n/4
BCLKs
11, 12, 14
T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay
8.80
10.20
ns
13
T31: Address Strobe Output Valid Delay
2.27
4.23
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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