Intel XeonTM Processor MP
94
Datasheet
Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event
occurs. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. For the
Intel Xeon processor MP, the SLP# pin may only be asserted when all logical processors are in the
Stop-Grant state. SLP# assertions while the processors are not in the Stop-Grant state is out of
specification and may result in illegal operation.
7.2.6
Bus Response During Low Power States
While in AutoHALT Power Down and Stop-Grant states, the processor will process a system bus
snoop.
When the processor is in the Sleep state, it will not respond to interrupts or snoop transactions.
7.3
Thermal Monitor
Thermal Monitor is a new feature found in the processor that allows system designers to design
lower cost thermal solutions, without compromising system integrity or reliability. By using a
factory-tuned, precision on-die temperature sensor, and a fast acting thermal control circuit (TCC),
the processor, without the aid of any additional software or hardware, can control the processors
die temperature within factory specifications under typical real-world operating conditions.
Thermal Monitor thus allows the processor and system thermal solutions to be designed much
closer to the power envelopes of real applications, instead of being designed to the much higher
maximum processor power envelopes.
Thermal Monitor controls the processor temperature by modulating (starting and stopping) the
internal processor core clocks. The processor clocks are modulated when the thermal control
circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC. Automatic mode
and On-Demand mode. Automatic mode is required for the processor to operate within
specifications and must first be enabled via BIOS. Once automatic mode is enabled, the TCC
will activate only when the internal die temperature is very near the temperature limits of the
processor. When the TCC is enabled, and a high temperature situation exists (i.e. TCC is active),
the clocks will be modulated by alternately turning the clocks off and on at an approximate 50%
duty cycle. Clocks will not be off or on more than 3.0
s when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A small
amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC
when the processor temperature is near the trip point. Once the temperature has returned to a non-
critical level, and the hysteresis timer has expired, modulation ceases and the TCC goes inactive.
Processor performance will be decrease by approximately 50% when the TCC is active (assuming
a 50% duty cycle), however, with a properly designed and characterised thermal solution the TCC
most likely will only be activated briefly during the most power intensive applications while at
maximum chassis ambient temperature within the chassis.
For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic
mode does not require any additional hardware, software drivers or interrupt handling routines.
The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor
Control Register is written to a “1” the TCC will be activated immediately, independent of the
processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the
clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control
Register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in On-Demand
mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in
12.5% increments. On-Demand mode may be used at the same time Automatic mode is enabled,