Intel XeonTM Processor MP
98
Datasheet
7.4.2
Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which may be
used for other data at the system or processor vendor’s discretion. The data in this EEPROM, once
programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a
weak pull-down (10 K
) toallow the EEPROM tobe programmedin systems with no
implementation of this signal. The Scratch EEPROM resides in the upper half of the memory
component (addresses 80 - FFh). The lower half comprises the Processor Information ROM
(address 00 - 7Fh), which is permanently write protected by Intel.
2B - 30h
48
Reserved
Reserved for future use.
31h
8
Checksum
1 byte checksum
Package Data:
32 - 35h
32
Package Revision
Four 8-bit ASCII characters
36h
8
Reserved
Reserved for future use
37h
8
Checksum
1 byte checksum
Part Number Data:
38 - 3Eh
56
Processor Part Number
Seven 8-bit ASCII characters
3F - 4Ch
112
Processor BOM ID
Fourteen 8-bit ASCII characters
4D - 54h
64
Processor Electronic Signature
64-bit identification number
55 - 6Eh
208
Reserved
Reserved for future use
6Fh
8
Checksum
1 byte checksum
Thermal Ref. Data:
70h
8
Thermal Reference Byte
71 - 72h
16
Reserved
Reserved for future use
73h
8
Checksum
1 byte checksum
Feature Data:
74 - 77h
32
Processor Core Feature Flags
From CPUID function 1, EDX contents
78h
8
Processor Feature Flags
[7] = Reserved
[6] = Serial Signature
[5] = Electronic Signature Present 1
[4] = Thermal Sense Device Present
[3] = Thermal Reference Byte Present
[2]=OEMEEPROMPresent
[1] = Core VID Present
[0] = L3 Cache Present
79-7Bh
24
Additional Processor Feature
Flags
Reserved
7Ch
8
Reserved
Reserved for future use
7Dh
8
Checksum
1 byte checksum
Other Data:
7E - 7Fh
16
Reserved
Reserved for future use
Table 36. Processor Information ROM Format (Page 2 of 2)
Offset/Section
# of Bits
Function
Notes