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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 38/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
28
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Parameter will be measured at 56 mA (for use with system inputs).
3. All outputs are open-drain.
4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality
specifications in Chapter 3.0.
5. The VCC referred to in these specifications refers to instantaneous VCC.
6. The maximum output current for asynchronous GTL+ signals are not specified into the test load shown in Figure 3.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All DC specifications for the SMBus signal group are measured at the processor pins.
4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum
rise and fall times for SMBus signals.
2.12
AGTL+ System Bus Specifications
Routing topologies are dependent on the number of processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines. In most cases, termination
resistors are not required as these are integrated into the processor silicon, see Table 4 for details on
which AGTL+ signals do not include on-die termination.The termination resistors are enabled or
disabled through the ODTEN pin. To enable termination, this pin should be pulled up to V
CC
through a resistor and to disable termination, this pin should be pulled down to VSS through a
resistor. The processor's on-die termination must be enabled for the end agent only. Please refer to
Table 12 for termination resistor values.
Table 10. Asynchronous GTL+ Signal Groups DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
VIL
Input Low Voltage
-0.150
GTLREF - (0.1 * VCC/1.3)
V
5
VIH
Input High Voltage
GTLREF +
(0.1*VCC/1.3)
VCC
V4, 5
VOL
Output Low Voltage
-0.150
0.400
V
2
VOH
Output High Voltage
N/A
VCC
V3, 4, 5
IOL
Output Low Current
56
mA
6
ILI
Input Leakage Current
N/A
± 100
A
ILO
Output Leakage Current
N/A
± 100
A
Table 11. SMBus Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1,2, 3
VIL
Input Low Voltage
-0.30
0.30 * SM_VCC
V
VIH
Input High Voltage
0.70 * SM_VCC
3.465
V
VOL
Output Low Voltage
0
0.400
V
IOL
Output Low Current
N/A
3.0
mA
ILI
Input Leakage Current
N/A
± 10
A
ILO
Output Leakage Current
N/A
± 10
A
CSMB
SMBus Pin Capacitance
15.0
pF
4
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