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| 型号： | YF80528KC017512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 54/116页 |
| 文件大小： | 2277K |
| 代理商： | YF80528KC017512 |
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Intel XeonTM Processor MP
42
Datasheet
3.2
System Bus Signal Quality Specifications and
Measurement Guidelines
3.2.1
Ringback Guidelines
Many scenarios have been simulated to generate a set of system bus layout guidelines which are
available in the appropriate platform design guidelines.
Table 21 provides the signal quality specifications for the AGTL+ and asynchronous GTL+ signal
groups. Table 22 demonstrates the signal quality specifications for the TAP signal group. These
specifications are for use in simulating signal quality at the processor core pads
Maximum allowable overshoot and undershoot specifications for a given duration of time are
(high-to-low transitions).
The TAP signal group includes hysteresis on the input buffers and thus has relaxed ringback
requirements when compared to the other buffer types. Figure 19 shows the system bus ringback
tolerance for low-to-high transitions and Figure 20 for high-to-low transitions. The hysteresis
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all Intel XeonTM processor MP frequencies
and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.
4. All values specified by design characterization.
Figure 16. BCLK[1:0] Signal Integrity Waveform
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
Table 21. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups
Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
AGTL+, Async GTL+
Low
→ High
GTLREF + 0.100
V
1,2,3,4,5,6,7
AGTL+, Async GTL+
High
→ Low
GTLREF - 0.100
V
1,2,3,4,5,6,7
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相关代理商/技术参数 |
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