MOTOROLA
MC68330 USER’S MANUAL
2- 3
Table 2-1. Signal Index
Signal Name
Mnemonic
Function
Address Bus
A23–A0
Lower 24 bits of address bus
Address Bus/ Port A7–A0/
IACK7–
IACK1
A31–A24
Upper eight bits of address bus, parallel I/O port, or interrupt
acknowledge lines
Data Bus
D15–D0
16-bit data bus used to transfer byte or word data
Function Codes
FC2–FC0
Identifies the processor state and the address space of the
current bus cycle
Chip Select /
AVEC
CS3–
CS0
Enables peripherals at programmed addresses or provides
automatic vector request (
CS0) during an interrupt
acknowledge cycle
Bus Request
BR
Indicates that an external device requires bus mastership
Bus Grant
BG
Indicates that current bus cycle is complete and the
MC68330 has relinquished the bus
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus
mastership
Data and Size Acknowledge
DSACK1,
DSACK0
Provides asynchronous data transfers and dynamic bus
sizing
Byte Write Enable
UWE, LWE
Provides an enable signal for byte writes to external devices,
when using a 16-bit port
Read-Modify-Write Cycle
RMC
Identifies the bus cycle as part of an indivisible read-modify-
write operation
Address Strobe
AS
Indicates that a valid address is on the address bus
Data Strobe
DS
During a read cycle,
DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus.
Size
SIZ1, SIZ0
Indicates the number of bytes remaining to be transferred for
this cycle
Read/Write
R/
W
Indicates the direction of data transfer on the bus
Interrupt Request Level/
Port B7 – B1
IRQ7 – IRQ1
Provides an interrupt priority level to the CPU32 or provides
parallel I/O
Reset
RESET
System reset
Halt
HALT
Suspend external bus activity
Bus Error
BERR
Indicates an erroneous bus operation is being attempted
System Clock Out
CLKOUT
Internal system clock output
Crystal Oscillator
EXTAL, XTAL
Connections for an external crystal to the internal oscillator
circuit
External Filter Capacitor
XFC
Connection pin for an external capacitor to filter the circuit of
the phase-locked loop
Clock Mode Select/Port B0
MODCK
Selects the source of the internal system clock or furnishes a
parallel I/O bit
Instruction Fetch
IFETCH
Indicates when the CPU32 is performing an instruction word
prefetch and when the instruction pipeline has been flushed
Instruction Pipe
IPIPE
Tracks movement of words through the instruction pipeline
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU32
Freeze
FREEZE
Indicates that the CPU32 has entered background debug
mode
Test Clock
TCK
Provides a clock for IEEE 1149.1 test logic
Test Mode Select
TMS
Controls test mode operations
Test Data In
TDI
Shifts in test instructions and test data
Test Data Out
TDO
Shifts out test instructions and test data
Synchronizer Power
VCCSYN
Quiet power supply to VCO; also used to control synthesizer
mode after reset.
System Power Supply and Return
VCC, GND
Power supply and return to the MC68330