MOTOROLA
MC68330 USER’S MANUAL
7-5
7.2.1 Startup
RESET is asserted by the MC68330 during the time in which VCC is ramping up, the
VCO is locking onto the frequency, and the MC68330 is going through the reset
operation. After
RESET is negated, four bus cycles are run, with CS0 being asserted to
fetch the 32-bit program counter (PC) and the 32-bit stack pointer (SP) from the boot
ROM. Until programmed differently,
CS0 is a 16-bit-wide, three-wait-state chip select.
After the PC and the SP are fetched, the following programming steps should be
followed:
Initialize and set the valid bit in the module base address register (CPU space
address $0003FF00) with the desired base address for the SIM registers.
Initialize and set the valid bits in the necessary chip-select base address and
address mask registers. Following this step, other system resources requiring the
CSx signals can be accessed. Care must be exercised when changing the
address for
CS0. The address of the instruction following the MOVE instruction to
the
CS0 base address register must match the value of the PC at that time.
7.2.2 SIM Module Configuration
The order of the following SIM register initializations is not important; however, time can
be saved by initializing the clock synthesizer control register first to quickly increase to
the desired processor operating frequency. The module base address register must be
initialized prior to any of following steps.
Clock Synthesizer Control Register (SYNCR)
Set frequency control bits (W, X, Y) to specify frequency.
Select action taken during loss of crystal (RSTEN bit): activate a system reset or
operate in limp mode.
Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits).
Module Configuration Register (MCR)
If using the software watchdog and/or the periodic interrupt timer, select action
taken when FREEZE is asserted (FRZ bits).
Select whether
CS0 will be disabled and this bit function as an autovector input
(
AVEC), or CS0 will be enabled.
Select the show cycle action (SHEN bits).
Select the access privilege for the supervisor/user registers (SUPV bit).
Select the interrupt arbitration level for the SIM (IARB bits).
Autovector Register (AVR)
Select the desired external interrupt levels for internal autovectoring.
System Protection Control Register (SYPCR) (Note that this register can only be written
once after reset.)
Enable the software watchdog, if desired (SWE bit).