5- 106
MC68330 USER'S MANUAL
MOTOROLA
Assertion of
IPIPE for two clock cycles indicates the start of a new instruction and
subsequent replacement of data in IRC. This action causes a full advance of the pipeline
(IRB
IRC and IRA IRB). IRA is refilled during the next instruction fetch bus cycle.
Data loaded into IRA propagates automatically through subsequent empty pipeline stages.
Signals that show the progress of instructions through IRB and IRC are necessary to
accurately monitor pipeline operation. These signals are provided by IRA and IRB validity
bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set, and
the validity bit of the stage supplying the data is negated.
Because instruction execution is not timed to bus activity,
IPIPE is synchronized with the
system clock and not the bus. Figure 5-38 illustrates the timing in relation to the system
clock.
IPIPE
EXTENSION
WORD USED
INSTRUCTION
START
EXTENSION
WORD USED
INSTRUCTION
START
IRA
IRB
IRA
IRB
IRA
IRB
IRB IRC
IRA
IRB
CLKOUT
IRB IRC
Figure 5-38. Instruction Pipeline Timing Diagram
IPIPE should be sampled on the falling edge of the clock. The assertion of IPIPE for a
single cycle after one or more cycles of negation indicates use of the data in IRB (advance
of IRA into IRB). Assertion for two clock cycles indicates that a new instruction has started
(both IRB
IRC and IRA IRB transfers have occurred). Loading IRC always indicates
that an instruction is beginning execution — the opcode is loaded into IRC by the transfer.
In some cases, instructions using immediate addressing begin executing and initiate a
second pipeline advance at the same time.
IPIPE will not be negated between the two
indications, which implies the need for a state machine to track the state of
IPIPE. The
state machine can be resynchronized during periods of inactivity on the signal.
5.7.3.3 OPCODE TRACKING DURING LOOP MODE.
IPIPE and IFETCH continue to
work normally during loop mode.
IFETCH indicates all instruction fetches up through the
point that data begins recirculating within the instruction pipeline.
IPIPE continues to
signal the start of instructions and the use of extension words even though data is being
recirculated internally.
IFETCH returns to normal operation with the first fetch after exiting
loop mode.
5.8 INSTRUCTION EXECUTION TIMING
This section describes the instruction execution timing of the CPU32. External clock cycles
are used to provide accurate execution and operation timing guidelines, but not exact
timing for every possible circumstance. This approach is used because exact execution