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MC68330 USER’S MANUAL
MOTOROLA
This pin is used to add an external capacitor to the filter circuit of the phase-locked loop.
The capacitor should be connected between XFC and VCCSYN.
2.10.4 Clock Mode Select (MODCK)
This pin selects the source of the internal system clock during reset. After reset, it can be
programmed to be port B parallel I/O.
MODCK. The state of this active-high input signal during reset selects the source of the
internal system clock. If MODCK is high during reset, the internal voltage-controlled
oscillator (VCO) furnishes the system clock. If MODCK is low during reset, an external
frequency appearing at the EXTAL pin furnishes the system clock.
Port B0. This pin can be used as port B parallel I/O. Refer to 4.2.5.2 PORT B for more
information on parallel I/O signals.
2.11 INSTRUMENTATION AND EMULATION SIGNALS
These signals are used for test or software debugging.
2.11.1 Instruction Fetch (
IFETCH)
This active-low output signal indicates when the CPU32 is performing an instruction word
prefetch and when the instruction pipeline has been flushed. Refer to Section 5 CPU32
for information about
IFETCH.
2.11.2 Instruction Pipe (
IPIPE)
This active-low output signal is used to track movement of words through the instruction
pipeline. Refer to Section 5 CPU32 for information about
IPIPE.
2.11.3 Breakpoint (
BKPT)
This active-low input signal is used to signal a hardware breakpoint to the CPU32. Refer to
Section 5 CPU32 for information about
BKPT.
2.11.4 Freeze (FREEZE)
Assertion of this active-high output signal indicates the CPU32 has acknowledged a
breakpoint and has initiated background mode operation. See Section 5 CPU32 for more
information about FREEZE and background mode.
2.12 TEST SIGNALS
The following signals are used with the onboard test logic defined by the IEEE 1149.1
standard. See Section 6 IEEE 1149.1 Test Access Port for more information on the use
of these signals.
2.12.1 Test Clock (TCK)
This input provides a clock for onboard test logic defined by the IEEE 1149.1 standard.