MOTOROLA
MC68330 USER’S MANUAL
v
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
3.2.5
Synchronous Operation with
DSACKx...................................................... 3-14
3.2.6
Fast-Termination Cycles............................................................................... 3-15
3.3
Data Transfer Cycles..................................................................................... 3-16
3.3.1
Read Cycle...................................................................................................... 3-17
3.3.2
Write Cycle...................................................................................................... 3-18
3.3.3
Read-Modify-Write Cycle.............................................................................. 3-19
3.4
CPU Space Cycles........................................................................................ 3-22
3.4.1
Breakpoint Acknowledge Cycle.................................................................. 3-22
3.4.2
LPSTOP Broadcast Cycle............................................................................ 3-26
3.4.3
Module Base Address Register Access..................................................... 3-27
3.4.4
Interrupt Acknowledge Bus Cycles............................................................. 3-27
3.4.4.1
Interrupt Acknowledge Cycle — Terminated Normally........................... 3-27
3.4.4.2
Autovector Interrupt Acknowledge Cycle .................................................. 3-30
3.4.4.3
Spurious Interrupt Cycle............................................................................... 3-32
3.5
Bus Exception Control Cycles..................................................................... 3-33
3.5.1
Bus Errors........................................................................................................ 3-35
3.5.2
Retry Operation .............................................................................................. 3-37
3.5.3
Halt Operation ................................................................................................ 3-38
3.5.4
Double Bus Fault ........................................................................................... 3-40
3.6
Bus Arbitration................................................................................................ 3-40
3.6.1
Bus Request.................................................................................................... 3-43
3.6.2
Bus Grant......................................................................................................... 3-43
3.6.3
Bus Grant Acknowledge............................................................................... 3-43
3.6.4
Bus Arbitration Control.................................................................................. 3-43
3.6.5
Show Cycles................................................................................................... 3-45
3.7
Reset Operation ............................................................................................. 3-47
Section 4
System Integration Module
4.1
Module Overview..............................................................................................4-1
4.2
Module Operation.............................................................................................4-2
4.2.1
Module Base Address Register......................................................................4-2
4.2.2
System Configuration and Protection Function ..........................................4-3
4.2.2.1
System Configuration ......................................................................................4-5
4.2.2.2
Internal Bus Monitor .........................................................................................4-5
4.2.2.3
Double Bus Fault Monitor................................................................................4-5
4.2.2.4
Spurious Interrupt Monitor ..............................................................................4-5
4.2.2.5
Software Watchdog ..........................................................................................4-6
4.2.2.6
Periodic Interrupt Timer ...................................................................................4-6
4.2.2.6.1
Periodic Timer Period Calculation.................................................................4-7
4.2.2.6.2
Using the Periodic Timer as a Real-Time Clock .........................................4-8
4.2.2.7
Simultaneous Interrupts by Sources in the SIM40.....................................4-8
4.2.3
Clock Synthesizer.............................................................................................4-8
4.2.3.1
Phase Comparator and Filter ...................................................................... 4-11
4.2.3.2
Frequency Divider ......................................................................................... 4-11