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MOTOROLA
MC68330 USER'S MANUAL
4-15
Table 4-5. Port B Pin Assignment
Register
Pin Function
Signal
PPARB BIT = 0
PPARB BIT = 1
IRQ7
PORT B7
IRQ7
IRQ6
PORT B6
IRQ6
IRQ5
PORT B5
IRQ5
IRQ4
PORT B4
IRQ4
IRQ3
PORT B3
IRQ3
IRQ2
PORT B2
IRQ2
IRQ1
PORT B1
IRQ1
MODCK
PORT B0
MODCK
NOTE: MODCK has no function after reset.
4.2.6 Low-Power Stop
Executing the LPSTOP instruction provides reduced power consumption when the
MC68330 is idle, with only the SIM40 remaining active. Operation of the SIM40 clock
and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR
(see Table 4-3). LPSTOP disables the clock to the software watchdog in the low state.
The software watchdog remains stopped until the LPSTOP mode is ended and begins to
run again on the next rising clock edge.
NOTE
When the CPU32 executes the STOP instruction (as
opposed to LPSTOP), the software watchdog continues
to run. If the software watchdog is enabled, it issues a
reset or interrupt when timeout occurs.
The periodic interrupt timer does not respond to an LPSTOP instruction; thus, it can be
used to exit LPSTOP as long as the interrupt request level is higher than the CPU32
interrupt mask level. To stop the periodic interrupt timer while in LPSTOP, the PITR must
be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus
fault monitor, and spurious interrupt monitor are all inactive during LPSTOP.
If an external device requires additional time to prepare for entry into LPSTOP mode,
entry can be delayed by asserting
HALT (see 3.4.2 LPSTOP Broadcast Cycle).
4.2.7 Freeze
FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode
enabled. Refer to Section 5 CPU32 for more information on the background mode.
When FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor
continue to operate normally. However, the software watchdog and the periodic interrupt
timer may be affected. Setting the FRZ1 bit in the MCR disables the software watchdog
when FREEZE is asserted, and setting the FRZ0 bit in the MCR disables the periodic
interrupt timer when FREEZE is asserted.