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MC68330 USER’S MANUAL
MOTOROLA
System Failure Protection:
— Software Watchdog Timer
— Periodic Interrupt Timer
— Spurious Interrupt, Double Bus Fault, and Bus Timeout Monitors
— Automatic Programmable Bus Termination
Up to 16 Discrete I/O Pins
Low-Power Operation:
— HCMOS Technology Reduces Power in Normal Operation
— LPSTOP Mode Provides Static State for Lower Standby Drain
Frequency: 0–25 MHz at 5-V Supply, Software Programmable
Package: 132-Pin Plastic Quad Flat Pack (PQFP)
1.1 CENTRAL PROCESSOR UNIT
The central processing unit of the MC68330 is the CPU32, an upward-compatible
M68000 Family member that excels in processing calculation-intensive algorithms and
supporting high-level languages. All MC68010 and most MC68020 enhancements, such
as virtual memory support, loop mode operation, instruction pipeline, and 32-bit
mathematical operations, are supported. Powerful addressing modes provide
compatibility with existing software programs and increase the efficiency of high-level
language compilers. New instructions, such as table lookup and interpolate and low
power stop, support the specific requirements for embedded control applications. Most
instructions can execute in half the number of clocks required by an MC68000, yielding
an overall 1.6 times performance of the same-speed MC68000.
1.2 SYSTEM INTEGRATION MODULE
The SIM40 includes an external interface and various functions that reduce the need for
external glue logic. The SIM40 contains system configuration and protection, the clock
synthesizer, four chip selects, and the external bus interface (EBI).
1.2.1 System Configuration and Protection
The system configuration and protection function controls system configuration and
provides maximum system safeguards. System protection is provided on the MC68330
by various monitors and timers, including the bus monitor, double bus fault monitor,
spurious interrupt monitor, software watchdog timer, and the periodic interrupt timer.
These system functions are integrated on the MC68330 to reduce board size and the
cost incurred with external components.
1.2.2 Clock Synthesizer
The system clock can be generated by an on-chip phase-locked loop (PLL) circuit to run
the device from a 32.768-kHz watch crystal. An external clock can also be used. The
system speed can be changed dynamically with the PLL, providing either high
performance or low power consumption under software control. With its fully static
HCMOS design, it is possible to completely stop the system clock in software while still
preserving the contents of the registers.