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MOTOROLA
MC68330 USER'S MANUAL
4-1
SECTION 4
SYSTEM INTEGRATION MODULE
The MC68330 system integration module (SIM40) consists of several functions that
control the system startup, initialization, configuration, and the external bus with a
minimum of external devices. It also provides the IEEE 1149.1 boundary scan
capabilities. The SIM40 functions include the following:
System Configuration and Protection
Clock Synthesizer
Chip Selects and Wait States
External Bus Interface
Bus Arbitration
Dynamic Bus Sizing
IEEE 1149.1 Test Access Port
4.1 MODULE OVERVIEW
The system configuration and protection function controls system configuration and
provides various monitors and timers, including the internal bus monitor, double bus fault
monitor, spurious interrupt monitor, software watchdog timer, and the periodic interrupt
timer.
The clock synthesizer generates the clock signals used by the SIM40 and the CPU32, as
well as the CLKOUT used by external devices.
The programmable chip-select function provides four chip-select signals that can enable
external memory and peripheral circuits, providing all handshaking and timing signals.
Each chip-select signal has an associated base address register and an address mask
register that contain the programmable characteristics of that chip select. Up to three wait
states can be programmed by bits in the address mask register.
The external bus interface (EBI) handles the transfer of information between the internal
CPU32 and memory, peripherals, or other processing elements in the external address
space. See Section 3 Bus Operation for further information.
The MC68330 dynamically interprets the port size of an addressed device during each
bus cycle, allowing operand transfers to or from 8- and 16-bit ports. The device signals
its port size and indicates completion of the bus cycle through the use of the
DSACKx
inputs. Dynamic bus sizing allows a programmer to write code that is not bus-width
specific. For a discussion on dynamic bus sizing see Section 3 Bus Operation.
The MC68330 includes dedicated user-accessible test logic that is fully compliant with
the IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture. Problems