MOTOROLA
MC68330 USER’S MANUAL
vii
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
5.1.8
Processing States.............................................................................................5-7
5.1.9
Privilege States.................................................................................................5-7
5.2
Architecture Summary .....................................................................................5-8
5.2.1
Programming Model.........................................................................................5-8
5.2.2
Registers.......................................................................................................... 5-10
5.2.3
Data Types...................................................................................................... 5-11
5.2.3.1
Organization in Registers............................................................................. 5-11
5.2.3.1.1
Data Registers ................................................................................................ 5-11
5.2.3.1.2
Address Register............................................................................................ 5-12
5.2.3.1.3
Control Registers ........................................................................................... 5-13
5.2.3.2
Organization in Memory ............................................................................... 5-13
5.3
Data Organization and Addressing Capabilities ..................................... 5-13
5.3.1
Program and Data References.................................................................... 5-15
5.3.2
Notation Conventions ................................................................................... 5-15
5.3.3
Implicit Reference .......................................................................................... 5-16
5.3.4
Effective Address ........................................................................................... 5-16
5.3.4.1
Register Direct Mode..................................................................................... 5-17
5.3.4.1.1
Data Register Direct ...................................................................................... 5-17
5.3.4.1.2
Address Register Direct................................................................................ 5-17
5.3.4.2
Memory Addressing Modes......................................................................... 5-17
5.3.4.2.1
Address Register Indirect ............................................................................. 5-17
5.3.4.2.2
Address Register Indirect with Postincrement.......................................... 5-17
5.3.4.2.3
Address Register Indirect with Predecrement .......................................... 5-18
5.3.4.2.4
Address Register Indirect with Displacement........................................... 5-18
5.3.4.2.5
Address Register Indirect with Index (8-Bit Displacement).................... 5-19
5.3.4.2.6
Address Register Indirect with Index (Base Displacement)................... 5-20
5.3.4.3
Special Addressing Modes.......................................................................... 5-20
5.3.4.3.1
Program Counter Indirect with Displacement........................................... 5-20
5.3.4.3.2
Program Counter Indirect with Index (8-Bit Displacement).................... 5-21
5.3.4.3.3
Program Counter Indirect with Index (Base Displacement)................... 5-21
5.3.4.3.4
Absolute Short Address................................................................................ 5-22
5.3.4.3.5
Absolute Long Address ................................................................................ 5-22
5.3.4.3.6
Immediate Data.............................................................................................. 5-23
5.3.4.4
Effective Address Encoding Summary ...................................................... 5-23
5.3.5
Programming View of Addressing Modes................................................. 5-25
5.3.5.1
Addressing Capabilities ............................................................................... 5-25
5.3.5.2
General Addressing Mode Summary ........................................................ 5-28
5.3.6
M68000 Family Addressing Capability...................................................... 5-28
5.3.7
Other Data Structures ................................................................................... 5-29
5.3.7.1
System Stack.................................................................................................. 5-29
5.3.7.2
User Stacks..................................................................................................... 5-30
5.3.7.3
Queues ............................................................................................................ 5-31
5.4
Instruction Set................................................................................................. 5-32
5.4.1
M68000 Family Compatibility...................................................................... 5-32
5.4.1.1
New Instructions............................................................................................. 5-33
5.4.1.1.1
Low-Power Stop (LPSTOP)......................................................................... 5-33