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MC68330 USER’S MANUAL
MOTOROLA
The data strobe is an output timing signal that applies to the data bus. For a read cycle,
the MC68330 asserts
DS and AS simultaneously to signal the external device to place
data on the bus. For a write cycle,
DS signals to the external device that the data to be
written is valid on the bus. The MC68330 asserts
DS approximately one clock cycle after
the assertion of
AS during a write cycle.
3.1.7 Byte Write Enable (
UWE, LWE)
The upper write enable (
UWE) indicates that the upper eight bits of the data bus contains
valid data during a write cycle. The lower write enable (
LWE) indicates that the lower eight
bits of the data bus contains valid data during a write cycle. The equations of the byte
write enables are as follows:
UWE = R/W + AS + A0
LWE = R/W + AS + (A0
× SIZ0)
These signals have the same timing as
AS, and are only valid when writing to a 16-bit
port.
3.1.8 Bus Cycle Termination Signals
The following signals can terminate a bus cycle.
3.1.8.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS (
DSACK1 AND
DSACK0). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part
of the bus protocol. During a read cycle, this signals the MC68330 to terminate the bus
cycle and to latch the data. During a write cycle, this indicates that the external device has
successfully stored the data and that the cycle may terminate. These signals also indicate
to the MC68330 the size of the port for the bus cycle just completed (see Table 3-3). Refer
to 3.3.1 Read Cycle for timing relationships of
DSACK1 and DSACK0.
Additionally, the system integration module (SIM40) can be programmed to internally
generate
DSACK1 and DSACK0 for external accesses, eliminating logic required to
generate these signals. The SIM40 can alternatively be programmed to generate a fast
termination, providing a two-cycle external access. Refer to 3.2.6 Fast-Termination
Cycles for additional information on these cycles.
3.1.8.2 BUS ERROR (
BERR). This signal is also a bus cycle termination indicator and can
be used in the absence of
DSACKx to indicate a bus error condition. BERR can also be
asserted in conjunction with
DSACKx to indicate a bus error condition, provided it meets
the appropriate timing described in this section and in MC68330/D,
MC68330 Technical
Summary. Additionally,
BERR and HALT can be asserted together to indicate a retry
termination. Refer to 3.5 Bus Exception Control Cycles for additional information on the
use of these signals.
The internal bus monitor can be used to generate the
BERR signal for internal and
internal-to-external transfers in all the following descriptions. If the bus cycles of an
external bus master are to be monitored, external
BERR generation must be provided
since the internal
BERR monitor has no information about transfers initiated by an external
bus master.