MOTOROLA
MC68330 USER'S MANUAL
4-3
diagram. The SIM40 address range, fixed within the relocatable 4K-byte memory block,
is $000–$07F.
4.2.2 System Configuration and Protection Function
The SIM40 allows the user to control certain features of system configuration by writing
bits in the module configuration register (MCR). This register also contains read-only
status bits that show the state of the SIM40.
All M68000 Family members are designed to provide maximum system safeguards. As
an extension of the family, the MC68330 promotes the same basic concepts of
safeguarded design present in all M68000 members. In addition, many functions that
normally must be provided by external circuits are incorporated in this device. The
following features are provided in the system configuration and protection function:
SIM40 Configuration
The SIM40 allows the user to configure the system to the particular requirements.
The functions include control of FREEZE and show cycle operation, the function of
the
CS3–CS0 signals, the access privilege of the supervisor/user registers, the
level of interrupt arbitration, and automatic autovectoring for external interrupts.
Reset Status
The reset status register provides the user with information on the cause of the
most recent reset. The possible causes include: external, power-up, software
watchdog, double bus fault, loss of clock, and reset instruction.
Internal Bus Monitor
The SIM40 provides an internal bus monitor to monitor the data and size
acknowledge (DSACK) response time for all internal bus accesses. An option
allows the monitoring of external bus accesses. For external bus accesses, four
selectable response times are provided to allow for variations in response speed
of memory and peripherals used in the system. A bus error signal is asserted in-
ternally if the DSACK response limit is exceeded.
BERR is not asserted externally.
This monitor can be disabled for external bus cyles only.
Double Bus Fault Monitor
The double bus fault monitor causes a reset to occur if the internal HALT is
asserted by the CPU32, indicating a double bus fault. A double bus fault results
when a bus or address error occurs during the exception processing sequence for
a previous bus or address error, a reset, or while the CPU is loading information
from a bus error stack frame during an RTE instruction. This function can be
disabled. See Section 3 Bus Operation for more information.
Spurious Interrupt Monitor
If no interrupt arbitration occurs during an interrupt acknowledge cycle (IACK), the
bus error signal is asserted internally.
Software Watchdog
The software watchdog asserts reset or a level 7 interrupt (as selected by the
system protection and control register) if the software fails to service the software
watchdog for a designated period of time (i.e., because it is trapped in a loop or
lost). There are eight selectable timeout periods. This function can be disabled.