MOTOROLA
MC68330 USER'S MANUAL
5- 25
Table 5-3. Effective Addressing Mode Categories
Addressing Modes
Code
Register
Data
Memory
Control
Alterable
Syntax
Data Register Direct
000
reg. no.
X
—
X
Dn
Address Register Direct
001
reg. no.
—
X
An
Address Register Indirect
010
reg. no.
X
(An)
Address Register Indirect with
Postincrement
011
reg. no.
X
—
X
(An) +
Address Register Indirect with
Predecrement
100
reg. no.
X
—
X
– (An)
Address Register Indirect with
Displacement
101
reg.no.
X
(d16, An)
Address Register Indirect with Index
(8-Bit Displacemment)
110
reg. no.
X
(d8, An, Xn)
Address Register Indirect with Index
(Base Displacement)
110
reg. no.
X
(bd, An, Xn)
Absolute Short
111
000
X
(xxx).W
Absolute Long
111
001
X
(xxx).L
Program Counter Indirect with
Displacement
111
010
X
—
X
(d16 , PC)
Program Counter Indirect with Index
(8-Bit Displacement)
111
011
X
—
X
(d8, PC, Xn)
Program Counter Indirect with Index
(Base Displacement)
111
011
X
—
X
(bd, PC, Xn)
Immediate
111
100
X
—
#(data)
5.3.5 Programming View of Addressing Modes
Extensions to indexed addressing modes, indirection, and full 32-bit displacements
provide additional programming capabilities for the CPU32. The following paragraphs
describe addressing techniques and summarize addressing modes from a programming
point of view.
5.3.5.1 ADDRESSING CAPABILITIES. In the CPU32, setting the base register suppress
(BS) bit in the full format extension word (see Figure 5-10) suppresses use of the base
address register in calculating the EA, allowing any index register to be used in place of
the base register. Because any data register can be an index register, this provides a data
register indirect form (Dn). This mode could also be called register indirect (Rn) because
either a data register or an address register can be used to address memory — an
extension of M68000 Family addressing capability.
The ability to specify the size and scale of an index register (Xn.SIZE
SCALE) in these
modes provides additional addressing flexibility. When using the SIZE parameter, either
the entire contents of the index register can be used, or the least significant word can be
sign extended to provide a 32-bit index value (see Figure 5-11).